Search

Daniel H. Pan

Examiner (ID: 6004, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2315, 2182, 2783, 2899, 2302, 2183
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6363863 [patent_doc_number] => 20100250902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'Tracking Deallocated Load Instructions Using a Dependence Matrix' [patent_app_type] => utility [patent_app_number] => 12/410024 [patent_app_country] => US [patent_app_date] => 2009-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20100250902.pdf [firstpage_image] =>[orig_patent_app_number] => 12410024 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/410024
Tracking deallocated load instructions using a dependence matrix Mar 23, 2009 Issued
Array ( [id] => 6363853 [patent_doc_number] => 20100250900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'DEPENDENCY TRACKING FOR ENABLING SUCCESSIVE PROCESSOR INSTRUCTIONS TO ISSUE' [patent_app_type] => utility [patent_app_number] => 12/409934 [patent_app_country] => US [patent_app_date] => 2009-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5453 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20100250900.pdf [firstpage_image] =>[orig_patent_app_number] => 12409934 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/409934
Dependency tracking for enabling successive processor instructions to issue Mar 23, 2009 Issued
Array ( [id] => 7768159 [patent_doc_number] => 08117424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Systems, devices, and/or methods for managing programmable logic controller processing' [patent_app_type] => utility [patent_app_number] => 12/209561 [patent_app_country] => US [patent_app_date] => 2008-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7832 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/117/08117424.pdf [firstpage_image] =>[orig_patent_app_number] => 12209561 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/209561
Systems, devices, and/or methods for managing programmable logic controller processing Sep 11, 2008 Issued
Array ( [id] => 7746326 [patent_doc_number] => 08108652 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-31 [patent_title] => 'Vector processing with high execution throughput' [patent_app_type] => utility [patent_app_number] => 12/207645 [patent_app_country] => US [patent_app_date] => 2008-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6051 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/108/08108652.pdf [firstpage_image] =>[orig_patent_app_number] => 12207645 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/207645
Vector processing with high execution throughput Sep 9, 2008 Issued
Array ( [id] => 6619760 [patent_doc_number] => 20100064118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'Method and Apparatus for Reducing Latency Associated with Executing Multiple Instruction Groups' [patent_app_type] => utility [patent_app_number] => 12/208152 [patent_app_country] => US [patent_app_date] => 2008-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4569 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20100064118.pdf [firstpage_image] =>[orig_patent_app_number] => 12208152 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/208152
Method and Apparatus for Reducing Latency Associated with Executing Multiple Instruction Groups Sep 9, 2008 Abandoned
Array ( [id] => 7734557 [patent_doc_number] => 08103857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Microprocessor control apparatus as well as method and program for the same' [patent_app_type] => utility [patent_app_number] => 12/206108 [patent_app_country] => US [patent_app_date] => 2008-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8681 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/103/08103857.pdf [firstpage_image] =>[orig_patent_app_number] => 12206108 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/206108
Microprocessor control apparatus as well as method and program for the same Sep 7, 2008 Issued
Array ( [id] => 6619810 [patent_doc_number] => 20100064123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'HYBRID BRANCH PREDICTION DEVICE WITH SPARSE AND DENSE PREDICTION CACHES' [patent_app_type] => utility [patent_app_number] => 12/205429 [patent_app_country] => US [patent_app_date] => 2008-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8783 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20100064123.pdf [firstpage_image] =>[orig_patent_app_number] => 12205429 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/205429
Hybrid branch prediction device with sparse and dense prediction caches Sep 4, 2008 Issued
Array ( [id] => 6227615 [patent_doc_number] => 20100058039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'INSTRUCTION FETCH PIPELINE FOR SUPERSCALAR DIGITAL SIGNAL PROCESSORS AND METHOD OF OPERATION THEREOF' [patent_app_type] => utility [patent_app_number] => 12/204769 [patent_app_country] => US [patent_app_date] => 2008-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5439 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20100058039.pdf [firstpage_image] =>[orig_patent_app_number] => 12204769 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/204769
Instruction fetch pipeline for superscalar digital signal processors and method of operation thereof Sep 3, 2008 Issued
Array ( [id] => 4641946 [patent_doc_number] => 08019980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Branch target buffer system and method for storing target address' [patent_app_type] => utility [patent_app_number] => 12/202363 [patent_app_country] => US [patent_app_date] => 2008-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4870 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/019/08019980.pdf [firstpage_image] =>[orig_patent_app_number] => 12202363 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/202363
Branch target buffer system and method for storing target address Aug 31, 2008 Issued
Array ( [id] => 7813404 [patent_doc_number] => 08135942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'System and method for double-issue instructions using a dependency matrix and a side issue queue' [patent_app_type] => utility [patent_app_number] => 12/199971 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8803 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/135/08135942.pdf [firstpage_image] =>[orig_patent_app_number] => 12199971 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/199971
System and method for double-issue instructions using a dependency matrix and a side issue queue Aug 27, 2008 Issued
Array ( [id] => 5326163 [patent_doc_number] => 20090064153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'COMMAND SELECTION METHOD AND ITS APPARATUS, COMMAND THROW METHOD AND ITS APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/199447 [patent_app_country] => US [patent_app_date] => 2008-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5622 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20090064153.pdf [firstpage_image] =>[orig_patent_app_number] => 12199447 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/199447
Command selection method and its apparatus Aug 26, 2008 Issued
Array ( [id] => 4951081 [patent_doc_number] => 20080307207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'DATA EXCHANGE AND COMMUNICATION BETWEEN EXECUTION UNITS IN A PARALLEL PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/192813 [patent_app_country] => US [patent_app_date] => 2008-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20080307207.pdf [firstpage_image] =>[orig_patent_app_number] => 12192813 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/192813
Data exchange and communication between execution units in a parallel processor Aug 14, 2008 Issued
Array ( [id] => 4572608 [patent_doc_number] => 07962719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture' [patent_app_type] => utility [patent_app_number] => 12/187746 [patent_app_country] => US [patent_app_date] => 2008-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 38 [patent_no_of_words] => 5819 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/962/07962719.pdf [firstpage_image] =>[orig_patent_app_number] => 12187746 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/187746
Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture Aug 6, 2008 Issued
Array ( [id] => 5430473 [patent_doc_number] => 20090089783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'PARTIAL ORDER REDUCTION USING GUARDED INDEPENDENCE RELATIONS' [patent_app_type] => utility [patent_app_number] => 12/181665 [patent_app_country] => US [patent_app_date] => 2008-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5670 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20090089783.pdf [firstpage_image] =>[orig_patent_app_number] => 12181665 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/181665
Partial order reduction using guarded independence relations Jul 28, 2008 Issued
Array ( [id] => 7706603 [patent_doc_number] => 08091086 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-03 [patent_title] => 'System and method for virtualization using an open bus hypervisor' [patent_app_type] => utility [patent_app_number] => 12/176085 [patent_app_country] => US [patent_app_date] => 2008-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8344 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/091/08091086.pdf [firstpage_image] =>[orig_patent_app_number] => 12176085 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/176085
System and method for virtualization using an open bus hypervisor Jul 17, 2008 Issued
Array ( [id] => 6538106 [patent_doc_number] => 20100287561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'DEVICE FOR AND METHOD OF WEIGHTED-REGION CYCLE ACCOUNTING FOR MULTI-THREADED PROCESSOR CORES' [patent_app_type] => utility [patent_app_number] => 12/173771 [patent_app_country] => US [patent_app_date] => 2008-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8131 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20100287561.pdf [firstpage_image] =>[orig_patent_app_number] => 12173771 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/173771
Weighted-region cycle accounting for multi-threaded processor cores Jul 14, 2008 Issued
Array ( [id] => 7542878 [patent_doc_number] => 08060727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Microprogrammed processor having mutiple processor cores using time-shared access to a microprogram control store' [patent_app_type] => utility [patent_app_number] => 12/143075 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4035 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/060/08060727.pdf [firstpage_image] =>[orig_patent_app_number] => 12143075 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/143075
Microprogrammed processor having mutiple processor cores using time-shared access to a microprogram control store Jun 19, 2008 Issued
Array ( [id] => 4522354 [patent_doc_number] => 07917739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Storage medium storing calculation processing visualization program, calculation processing visualization apparatus, and calculation processing visualization method' [patent_app_type] => utility [patent_app_number] => 12/142499 [patent_app_country] => US [patent_app_date] => 2008-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7024 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/917/07917739.pdf [firstpage_image] =>[orig_patent_app_number] => 12142499 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/142499
Storage medium storing calculation processing visualization program, calculation processing visualization apparatus, and calculation processing visualization method Jun 18, 2008 Issued
Array ( [id] => 4447449 [patent_doc_number] => 07930521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-04-19 [patent_title] => 'Reducing multiplexer circuitry associated with a processor' [patent_app_type] => utility [patent_app_number] => 12/137406 [patent_app_country] => US [patent_app_date] => 2008-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6162 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930521.pdf [firstpage_image] =>[orig_patent_app_number] => 12137406 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/137406
Reducing multiplexer circuitry associated with a processor Jun 10, 2008 Issued
Array ( [id] => 5332701 [patent_doc_number] => 20090113178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Microprocessor based on event-processing instruction set and event-processing method using the same' [patent_app_type] => utility [patent_app_number] => 12/155833 [patent_app_country] => US [patent_app_date] => 2008-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5382 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20090113178.pdf [firstpage_image] =>[orig_patent_app_number] => 12155833 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/155833
Microprocessor based on event-processing instruction set and event-processing method using the same Jun 9, 2008 Issued
Menu