Daniel H. Pan

Array ( [id] => 4530409 [patent_doc_number] => 07913063 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-22 [patent_title] => 'System and method for performance based call distribution' [patent_app_type] => utility [patent_app_number] => 12/132259 [patent_app_country] => US [patent_app_date] => 2008-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/913/07913063.pdf [firstpage_image] =>[orig_patent_app_number] => 12132259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5491990 [patent_doc_number] => 20090293061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'Structural Power Reduction in Multithreaded Processor' [patent_app_type] => utility [patent_app_number] => 12/125278 [patent_app_country] => US [patent_app_date] => 2008-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10816 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20090293061.pdf [firstpage_image] =>[orig_patent_app_number] => 12125278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4498832 [patent_doc_number] => 07886132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Predication support in an out-of-order processor by selectively executing ambiguously renamed write operations' [patent_app_type] => utility [patent_app_number] => 12/123046 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4320 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/886/07886132.pdf [firstpage_image] =>[orig_patent_app_number] => 12123046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5381399 [patent_doc_number] => 20090193238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'Reconfigurable apparatus and method for providing multiple modes' [patent_app_type] => utility [patent_app_number] => 12/153409 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4776 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20090193238.pdf [firstpage_image] =>[orig_patent_app_number] => 12153409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4793906 [patent_doc_number] => 20080294880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'CUSTOMIZATION OF A MICROPROCESSOR AND DATA PROTECTION METHOD' [patent_app_type] => utility [patent_app_number] => 12/122742 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2942 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20080294880.pdf [firstpage_image] =>[orig_patent_app_number] => 12122742 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4472207 [patent_doc_number] => 07937560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Processor pipeline architecture logic state retention systems and methods' [patent_app_type] => utility [patent_app_number] => 12/121292 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4747 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/937/07937560.pdf [firstpage_image] =>[orig_patent_app_number] => 12121292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5491821 [patent_doc_number] => 20090292892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'Method to Reduce Power Consumption of a Register File with Multi SMT Support' [patent_app_type] => utility [patent_app_number] => 12/120958 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3499 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20090292892.pdf [firstpage_image] =>[orig_patent_app_number] => 12120958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4592803 [patent_doc_number] => 07853779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Methods and apparatus for scalable array processor interrupt detection and response' [patent_app_type] => utility [patent_app_number] => 12/120543 [patent_app_country] => US [patent_app_date] => 2008-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 13646 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853779.pdf [firstpage_image] =>[orig_patent_app_number] => 12120543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5317623 [patent_doc_number] => 20090282221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'Preferential Dispatching Of Computer Program Instructions' [patent_app_type] => utility [patent_app_number] => 12/118298 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14241 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282221.pdf [firstpage_image] =>[orig_patent_app_number] => 12118298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4508214 [patent_doc_number] => 07958340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Monitoring software pipeline performance on a network on chip' [patent_app_type] => utility [patent_app_number] => 12/117875 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12043 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958340.pdf [firstpage_image] =>[orig_patent_app_number] => 12117875 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4730427 [patent_doc_number] => 20080209162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION' [patent_app_type] => utility [patent_app_number] => 12/110491 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 34888 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209162.pdf [firstpage_image] =>[orig_patent_app_number] => 12110491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4730493 [patent_doc_number] => 20080209192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION' [patent_app_type] => utility [patent_app_number] => 12/110513 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 34886 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209192.pdf [firstpage_image] =>[orig_patent_app_number] => 12110513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7803699 [patent_doc_number] => 08131983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Method, apparatus and article of manufacture for timeout waits on locks' [patent_app_type] => utility [patent_app_number] => 12/111157 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4628 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/131/08131983.pdf [firstpage_image] =>[orig_patent_app_number] => 12111157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4678227 [patent_doc_number] => 20080215858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION' [patent_app_type] => utility [patent_app_number] => 12/110539 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 34888 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20080215858.pdf [firstpage_image] =>[orig_patent_app_number] => 12110539 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8208020 [patent_doc_number] => 08190862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Hardware device for processing the tasks of an algorithm in parallel' [patent_app_type] => utility [patent_app_number] => 12/109001 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3151 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/190/08190862.pdf [firstpage_image] =>[orig_patent_app_number] => 12109001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11306561 [patent_doc_number] => 09513959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Contention management for a hardware transactional memory' [patent_app_type] => utility [patent_app_number] => 12/149003 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6068 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12149003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4862813 [patent_doc_number] => 20080271028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'INFORMATION PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/106143 [patent_app_country] => US [patent_app_date] => 2008-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2436 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20080271028.pdf [firstpage_image] =>[orig_patent_app_number] => 12106143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4889220 [patent_doc_number] => 20080263552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'MULTITHREAD PROCESSOR AND METHOD OF SYNCHRONIZATION OPERATIONS AMONG THREADS TO BE USED IN SAME' [patent_app_type] => utility [patent_app_number] => 12/102151 [patent_app_country] => US [patent_app_date] => 2008-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2834 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263552.pdf [firstpage_image] =>[orig_patent_app_number] => 12102151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11306507 [patent_doc_number] => 09513905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Vector instructions to enable efficient synchronization and parallel reduction operations' [patent_app_type] => utility [patent_app_number] => 12/079774 [patent_app_country] => US [patent_app_date] => 2008-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7614 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12079774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4826468 [patent_doc_number] => 20080229319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Global Resource Allocation Control' [patent_app_type] => utility [patent_app_number] => 12/045258 [patent_app_country] => US [patent_app_date] => 2008-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3309 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229319.pdf [firstpage_image] =>[orig_patent_app_number] => 12045258 [rel_patent_id] =>[rel_patent_doc_number] =>)