Search

Daniel H. Pan

Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2302, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8208020 [patent_doc_number] => 08190862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Hardware device for processing the tasks of an algorithm in parallel' [patent_app_type] => utility [patent_app_number] => 12/109001 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3151 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/190/08190862.pdf [firstpage_image] =>[orig_patent_app_number] => 12109001 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/109001
Hardware device for processing the tasks of an algorithm in parallel Apr 23, 2008 Issued
Array ( [id] => 11306561 [patent_doc_number] => 09513959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Contention management for a hardware transactional memory' [patent_app_type] => utility [patent_app_number] => 12/149003 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6068 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12149003 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/149003
Contention management for a hardware transactional memory Apr 23, 2008 Issued
Array ( [id] => 4862813 [patent_doc_number] => 20080271028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'INFORMATION PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/106143 [patent_app_country] => US [patent_app_date] => 2008-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2436 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20080271028.pdf [firstpage_image] =>[orig_patent_app_number] => 12106143 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/106143
INFORMATION PROCESSING APPARATUS Apr 17, 2008 Abandoned
Array ( [id] => 4889220 [patent_doc_number] => 20080263552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'MULTITHREAD PROCESSOR AND METHOD OF SYNCHRONIZATION OPERATIONS AMONG THREADS TO BE USED IN SAME' [patent_app_type] => utility [patent_app_number] => 12/102151 [patent_app_country] => US [patent_app_date] => 2008-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2834 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263552.pdf [firstpage_image] =>[orig_patent_app_number] => 12102151 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/102151
Multithread processor and method of synchronization operations among threads to be used in same Apr 13, 2008 Issued
Array ( [id] => 11306507 [patent_doc_number] => 09513905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Vector instructions to enable efficient synchronization and parallel reduction operations' [patent_app_type] => utility [patent_app_number] => 12/079774 [patent_app_country] => US [patent_app_date] => 2008-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7614 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12079774 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/079774
Vector instructions to enable efficient synchronization and parallel reduction operations Mar 27, 2008 Issued
Array ( [id] => 4826468 [patent_doc_number] => 20080229319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Global Resource Allocation Control' [patent_app_type] => utility [patent_app_number] => 12/045258 [patent_app_country] => US [patent_app_date] => 2008-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3309 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229319.pdf [firstpage_image] =>[orig_patent_app_number] => 12045258 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/045258
Global Resource Allocation Control Mar 9, 2008 Abandoned
Array ( [id] => 4462366 [patent_doc_number] => 07895422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Selective postponement of branch target buffer (BTB) allocation' [patent_app_type] => utility [patent_app_number] => 12/040204 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 14663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/895/07895422.pdf [firstpage_image] =>[orig_patent_app_number] => 12040204 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/040204
Selective postponement of branch target buffer (BTB) allocation Feb 28, 2008 Issued
Array ( [id] => 4472236 [patent_doc_number] => 07937573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Metric for selective branch target buffer (BTB) allocation' [patent_app_type] => utility [patent_app_number] => 12/040210 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 14429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/937/07937573.pdf [firstpage_image] =>[orig_patent_app_number] => 12040210 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/040210
Metric for selective branch target buffer (BTB) allocation Feb 28, 2008 Issued
Array ( [id] => 7746340 [patent_doc_number] => 08108657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Handling floating point operations' [patent_app_type] => utility [patent_app_number] => 12/039375 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9691 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/108/08108657.pdf [firstpage_image] =>[orig_patent_app_number] => 12039375 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/039375
Handling floating point operations Feb 27, 2008 Issued
Array ( [id] => 7542877 [patent_doc_number] => 08060726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'SIMD microprocessor, image processing apparatus including same, and image processing method used therein' [patent_app_type] => utility [patent_app_number] => 12/038518 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8336 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/060/08060726.pdf [firstpage_image] =>[orig_patent_app_number] => 12038518 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/038518
SIMD microprocessor, image processing apparatus including same, and image processing method used therein Feb 26, 2008 Issued
Array ( [id] => 4448945 [patent_doc_number] => 07865697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Apparatus for and method of processor to processor communication for coprocessor functionality activation' [patent_app_type] => utility [patent_app_number] => 12/037948 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865697.pdf [firstpage_image] =>[orig_patent_app_number] => 12037948 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037948
Apparatus for and method of processor to processor communication for coprocessor functionality activation Feb 26, 2008 Issued
Array ( [id] => 4589539 [patent_doc_number] => 07861064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Method, system, and computer program product for selectively accelerating early instruction processing' [patent_app_type] => utility [patent_app_number] => 12/037861 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4407 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/861/07861064.pdf [firstpage_image] =>[orig_patent_app_number] => 12037861 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037861
Method, system, and computer program product for selectively accelerating early instruction processing Feb 25, 2008 Issued
Array ( [id] => 5516706 [patent_doc_number] => 20090217013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'METHOD AND APPARATUS FOR PROGRAMMATICALLY REWINDING A REGISTER INSIDE A TRANSACTION' [patent_app_type] => utility [patent_app_number] => 12/037636 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5618 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20090217013.pdf [firstpage_image] =>[orig_patent_app_number] => 12037636 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037636
Method and apparatus for programmatically rewinding a register inside a transaction Feb 25, 2008 Issued
Array ( [id] => 5516711 [patent_doc_number] => 20090217018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'METHODS, APPARATUS AND ARTICLES OF MANUFACTURE FOR REGAINING MEMORY CONSISTENCY AFTER A TRAP VIA TRANSACTIONAL MEMORY' [patent_app_type] => utility [patent_app_number] => 12/037888 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4336 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20090217018.pdf [firstpage_image] =>[orig_patent_app_number] => 12037888 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037888
Methods, apparatus and articles of manufacture for regaining memory consistency after a trap via transactional memory Feb 25, 2008 Issued
Array ( [id] => 8022631 [patent_doc_number] => 08140834 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'System, method and computer program product for providing a programmable quiesce filtering register' [patent_app_type] => utility [patent_app_number] => 12/037808 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5386 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/140/08140834.pdf [firstpage_image] =>[orig_patent_app_number] => 12037808 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037808
System, method and computer program product for providing a programmable quiesce filtering register Feb 25, 2008 Issued
Array ( [id] => 5528908 [patent_doc_number] => 20090198985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE WITH HASHED INDICES' [patent_app_type] => utility [patent_app_number] => 12/024219 [patent_app_country] => US [patent_app_date] => 2008-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5165 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20090198985.pdf [firstpage_image] =>[orig_patent_app_number] => 12024219 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/024219
Branch target address cache with hashed indices Jan 31, 2008 Issued
Array ( [id] => 8010827 [patent_doc_number] => 08086831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Indexed table circuit having reduced aliasing' [patent_app_type] => utility [patent_app_number] => 12/024241 [patent_app_country] => US [patent_app_date] => 2008-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5306 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086831.pdf [firstpage_image] =>[orig_patent_app_number] => 12024241 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/024241
Indexed table circuit having reduced aliasing Jan 31, 2008 Issued
Array ( [id] => 5528885 [patent_doc_number] => 20090198962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE INCLUDING ADDRESS TYPE TAG BIT' [patent_app_type] => utility [patent_app_number] => 12/024203 [patent_app_country] => US [patent_app_date] => 2008-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5353 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20090198962.pdf [firstpage_image] =>[orig_patent_app_number] => 12024203 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/024203
Branch target address cache including address type tag bit Jan 31, 2008 Issued
Array ( [id] => 4558894 [patent_doc_number] => 07877586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Branch target address cache selectively applying a delayed hit' [patent_app_type] => utility [patent_app_number] => 12/024190 [patent_app_country] => US [patent_app_date] => 2008-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6203 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/877/07877586.pdf [firstpage_image] =>[orig_patent_app_number] => 12024190 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/024190
Branch target address cache selectively applying a delayed hit Jan 31, 2008 Issued
Array ( [id] => 7532573 [patent_doc_number] => 07844807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Branch target address cache storing direct predictions' [patent_app_type] => utility [patent_app_number] => 12/024197 [patent_app_country] => US [patent_app_date] => 2008-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5732 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/844/07844807.pdf [firstpage_image] =>[orig_patent_app_number] => 12024197 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/024197
Branch target address cache storing direct predictions Jan 31, 2008 Issued
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