Search

Daniel H. Pan

Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2302, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5528882 [patent_doc_number] => 20090198959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'SCALABLE LINK STACK CONTROL METHOD WITH FULL SUPPORT FOR SPECULATIVE OPERATIONS' [patent_app_type] => utility [patent_app_number] => 12/023913 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20090198959.pdf [firstpage_image] =>[orig_patent_app_number] => 12023913 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/023913
Scalable link stack control method with full support for speculative operations Jan 30, 2008 Issued
Array ( [id] => 5528900 [patent_doc_number] => 20090198977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'Sharing Data in Internal and Memory Representations with Dynamic Data-Driven Conversion' [patent_app_type] => utility [patent_app_number] => 12/023768 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 18284 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20090198977.pdf [firstpage_image] =>[orig_patent_app_number] => 12023768 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/023768
Sharing data in internal and memory representations with dynamic data-driven conversion Jan 30, 2008 Issued
Array ( [id] => 4558825 [patent_doc_number] => 07877582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Multi-addressable register file' [patent_app_type] => utility [patent_app_number] => 12/023720 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12380 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/877/07877582.pdf [firstpage_image] =>[orig_patent_app_number] => 12023720 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/023720
Multi-addressable register file Jan 30, 2008 Issued
Array ( [id] => 5528890 [patent_doc_number] => 20090198967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'METHOD AND STRUCTURE FOR LOW LATENCY LOAD-TAGGED POINTER INSTRUCTION FOR COMPUTER MICROARCHITECHTURE' [patent_app_type] => utility [patent_app_number] => 12/023791 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5439 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20090198967.pdf [firstpage_image] =>[orig_patent_app_number] => 12023791 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/023791
Method and structure for low latency load-tagged pointer instruction for computer microarchitechture Jan 30, 2008 Issued
Array ( [id] => 7686423 [patent_doc_number] => 20090177868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'APPARATUS, SYSTEM, AND METHOD FOR DISCONTIGUOUS MULTIPLE ISSUE OF INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 11/969180 [patent_app_country] => US [patent_app_date] => 2008-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20090177868.pdf [firstpage_image] =>[orig_patent_app_number] => 11969180 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/969180
Apparatus, system, and method for discontiguous multiple issue of instructions Jan 2, 2008 Issued
Array ( [id] => 4549752 [patent_doc_number] => 07873819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-18 [patent_title] => 'Branch target buffer addressing in a data processor' [patent_app_type] => utility [patent_app_number] => 11/969116 [patent_app_country] => US [patent_app_date] => 2008-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9203 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 368 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/873/07873819.pdf [firstpage_image] =>[orig_patent_app_number] => 11969116 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/969116
Branch target buffer addressing in a data processor Jan 2, 2008 Issued
Array ( [id] => 37537 [patent_doc_number] => 07793080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Processing pipeline having parallel dispatch and method thereof' [patent_app_type] => utility [patent_app_number] => 11/967924 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7740 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/793/07793080.pdf [firstpage_image] =>[orig_patent_app_number] => 11967924 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967924
Processing pipeline having parallel dispatch and method thereof Dec 30, 2007 Issued
Array ( [id] => 8010815 [patent_doc_number] => 08086825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Processing pipeline having stage-specific thread selection and method thereof' [patent_app_type] => utility [patent_app_number] => 11/967923 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7834 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086825.pdf [firstpage_image] =>[orig_patent_app_number] => 11967923 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967923
Processing pipeline having stage-specific thread selection and method thereof Dec 30, 2007 Issued
12/004629 Programmable arithmetic logic unit cluster Dec 21, 2007 Abandoned
Array ( [id] => 4510805 [patent_doc_number] => 07949853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Two dimensional addressing of a matrix-vector register array' [patent_app_type] => utility [patent_app_number] => 11/950474 [patent_app_country] => US [patent_app_date] => 2007-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7222 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/949/07949853.pdf [firstpage_image] =>[orig_patent_app_number] => 11950474 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/950474
Two dimensional addressing of a matrix-vector register array Dec 4, 2007 Issued
Array ( [id] => 5565821 [patent_doc_number] => 20090138674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'ELECTRONIC SYSTEM FOR CHANGING NUMBER OF PIPELINE STAGES OF A PIPELINE' [patent_app_type] => utility [patent_app_number] => 11/944416 [patent_app_country] => US [patent_app_date] => 2007-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6298 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20090138674.pdf [firstpage_image] =>[orig_patent_app_number] => 11944416 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/944416
Electronic system and method for changing number of operation stages of a pipeline Nov 21, 2007 Issued
Array ( [id] => 7524980 [patent_doc_number] => 08028150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-27 [patent_title] => 'Runtime instruction decoding modification in a multi-processing array' [patent_app_type] => utility [patent_app_number] => 11/941847 [patent_app_country] => US [patent_app_date] => 2007-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2249 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/028/08028150.pdf [firstpage_image] =>[orig_patent_app_number] => 11941847 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/941847
Runtime instruction decoding modification in a multi-processing array Nov 15, 2007 Issued
Array ( [id] => 4616533 [patent_doc_number] => 07991986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Microprocessor starting to execute a computer program at a predetermined interval' [patent_app_type] => utility [patent_app_number] => 11/902365 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11832 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/991/07991986.pdf [firstpage_image] =>[orig_patent_app_number] => 11902365 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/902365
Microprocessor starting to execute a computer program at a predetermined interval Sep 19, 2007 Issued
Array ( [id] => 4641945 [patent_doc_number] => 08019979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Efficient implementation of branch intensive algorithms in VLIW and superscalar processors' [patent_app_type] => utility [patent_app_number] => 11/854003 [patent_app_country] => US [patent_app_date] => 2007-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4881 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/019/08019979.pdf [firstpage_image] =>[orig_patent_app_number] => 11854003 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/854003
Efficient implementation of branch intensive algorithms in VLIW and superscalar processors Sep 11, 2007 Issued
Array ( [id] => 8001147 [patent_doc_number] => 08082421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-20 [patent_title] => 'Program instruction rearrangement methods in computer' [patent_app_type] => utility [patent_app_number] => 11/849485 [patent_app_country] => US [patent_app_date] => 2007-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4465 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/082/08082421.pdf [firstpage_image] =>[orig_patent_app_number] => 11849485 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/849485
Program instruction rearrangement methods in computer Sep 3, 2007 Issued
Array ( [id] => 4911306 [patent_doc_number] => 20080022073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests' [patent_app_type] => utility [patent_app_number] => 11/888411 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7266 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20080022073.pdf [firstpage_image] =>[orig_patent_app_number] => 11888411 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/888411
Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests Jul 30, 2007 Issued
Array ( [id] => 4539867 [patent_doc_number] => 07953958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Architecture for joint detection hardware accelerator' [patent_app_type] => utility [patent_app_number] => 11/818055 [patent_app_country] => US [patent_app_date] => 2007-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 15304 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/953/07953958.pdf [firstpage_image] =>[orig_patent_app_number] => 11818055 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/818055
Architecture for joint detection hardware accelerator Jun 11, 2007 Issued
Array ( [id] => 4539867 [patent_doc_number] => 07953958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Architecture for joint detection hardware accelerator' [patent_app_type] => utility [patent_app_number] => 11/818055 [patent_app_country] => US [patent_app_date] => 2007-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 15304 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/953/07953958.pdf [firstpage_image] =>[orig_patent_app_number] => 11818055 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/818055
Architecture for joint detection hardware accelerator Jun 11, 2007 Issued
Array ( [id] => 4440959 [patent_doc_number] => 07971031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Data processing system and method' [patent_app_type] => utility [patent_app_number] => 11/754391 [patent_app_country] => US [patent_app_date] => 2007-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5900 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971031.pdf [firstpage_image] =>[orig_patent_app_number] => 11754391 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/754391
Data processing system and method May 28, 2007 Issued
Array ( [id] => 6616128 [patent_doc_number] => 20100293342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-18 [patent_title] => 'DATA PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/594715 [patent_app_country] => US [patent_app_date] => 2007-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 39816 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20100293342.pdf [firstpage_image] =>[orig_patent_app_number] => 12594715 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/594715
Data processing apparatus with instruction encodings to enable near and far memory access modes Apr 9, 2007 Issued
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