
Daniel H. Pan
Examiner (ID: 6004, Phone: (571)272-4172 , Office: P/2182 )
| Most Active Art Unit | 2182 |
| Art Unit(s) | 2315, 2182, 2783, 2899, 2302, 2183 |
| Total Applications | 1471 |
| Issued Applications | 1281 |
| Pending Applications | 50 |
| Abandoned Applications | 145 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8010815
[patent_doc_number] => 08086825
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-27
[patent_title] => 'Processing pipeline having stage-specific thread selection and method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/967923
[patent_app_country] => US
[patent_app_date] => 2007-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 7834
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/086/08086825.pdf
[firstpage_image] =>[orig_patent_app_number] => 11967923
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/967923 | Processing pipeline having stage-specific thread selection and method thereof | Dec 30, 2007 | Issued |
Array
(
[id] => 37537
[patent_doc_number] => 07793080
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-07
[patent_title] => 'Processing pipeline having parallel dispatch and method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/967924
[patent_app_country] => US
[patent_app_date] => 2007-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 7740
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/793/07793080.pdf
[firstpage_image] =>[orig_patent_app_number] => 11967924
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/967924 | Processing pipeline having parallel dispatch and method thereof | Dec 30, 2007 | Issued |
| 12/004629 | Programmable arithmetic logic unit cluster | Dec 21, 2007 | Abandoned |
Array
(
[id] => 4510805
[patent_doc_number] => 07949853
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-24
[patent_title] => 'Two dimensional addressing of a matrix-vector register array'
[patent_app_type] => utility
[patent_app_number] => 11/950474
[patent_app_country] => US
[patent_app_date] => 2007-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 7222
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 272
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/949/07949853.pdf
[firstpage_image] =>[orig_patent_app_number] => 11950474
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/950474 | Two dimensional addressing of a matrix-vector register array | Dec 4, 2007 | Issued |
Array
(
[id] => 5565821
[patent_doc_number] => 20090138674
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-28
[patent_title] => 'ELECTRONIC SYSTEM FOR CHANGING NUMBER OF PIPELINE STAGES OF A PIPELINE'
[patent_app_type] => utility
[patent_app_number] => 11/944416
[patent_app_country] => US
[patent_app_date] => 2007-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6298
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0138/20090138674.pdf
[firstpage_image] =>[orig_patent_app_number] => 11944416
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/944416 | Electronic system and method for changing number of operation stages of a pipeline | Nov 21, 2007 | Issued |
Array
(
[id] => 7524980
[patent_doc_number] => 08028150
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-09-27
[patent_title] => 'Runtime instruction decoding modification in a multi-processing array'
[patent_app_type] => utility
[patent_app_number] => 11/941847
[patent_app_country] => US
[patent_app_date] => 2007-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2249
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/028/08028150.pdf
[firstpage_image] =>[orig_patent_app_number] => 11941847
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/941847 | Runtime instruction decoding modification in a multi-processing array | Nov 15, 2007 | Issued |
Array
(
[id] => 4616533
[patent_doc_number] => 07991986
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-02
[patent_title] => 'Microprocessor starting to execute a computer program at a predetermined interval'
[patent_app_type] => utility
[patent_app_number] => 11/902365
[patent_app_country] => US
[patent_app_date] => 2007-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 11832
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/991/07991986.pdf
[firstpage_image] =>[orig_patent_app_number] => 11902365
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/902365 | Microprocessor starting to execute a computer program at a predetermined interval | Sep 19, 2007 | Issued |
Array
(
[id] => 4641945
[patent_doc_number] => 08019979
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-09-13
[patent_title] => 'Efficient implementation of branch intensive algorithms in VLIW and superscalar processors'
[patent_app_type] => utility
[patent_app_number] => 11/854003
[patent_app_country] => US
[patent_app_date] => 2007-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4881
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/019/08019979.pdf
[firstpage_image] =>[orig_patent_app_number] => 11854003
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/854003 | Efficient implementation of branch intensive algorithms in VLIW and superscalar processors | Sep 11, 2007 | Issued |
Array
(
[id] => 8001147
[patent_doc_number] => 08082421
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-20
[patent_title] => 'Program instruction rearrangement methods in computer'
[patent_app_type] => utility
[patent_app_number] => 11/849485
[patent_app_country] => US
[patent_app_date] => 2007-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4465
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/082/08082421.pdf
[firstpage_image] =>[orig_patent_app_number] => 11849485
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/849485 | Program instruction rearrangement methods in computer | Sep 3, 2007 | Issued |
Array
(
[id] => 4911306
[patent_doc_number] => 20080022073
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-24
[patent_title] => 'Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests'
[patent_app_type] => utility
[patent_app_number] => 11/888411
[patent_app_country] => US
[patent_app_date] => 2007-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 7266
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0022/20080022073.pdf
[firstpage_image] =>[orig_patent_app_number] => 11888411
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/888411 | Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests | Jul 30, 2007 | Issued |
Array
(
[id] => 4539867
[patent_doc_number] => 07953958
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-31
[patent_title] => 'Architecture for joint detection hardware accelerator'
[patent_app_type] => utility
[patent_app_number] => 11/818055
[patent_app_country] => US
[patent_app_date] => 2007-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 20
[patent_no_of_words] => 15304
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/953/07953958.pdf
[firstpage_image] =>[orig_patent_app_number] => 11818055
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/818055 | Architecture for joint detection hardware accelerator | Jun 11, 2007 | Issued |
Array
(
[id] => 4539867
[patent_doc_number] => 07953958
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-31
[patent_title] => 'Architecture for joint detection hardware accelerator'
[patent_app_type] => utility
[patent_app_number] => 11/818055
[patent_app_country] => US
[patent_app_date] => 2007-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 20
[patent_no_of_words] => 15304
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/953/07953958.pdf
[firstpage_image] =>[orig_patent_app_number] => 11818055
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/818055 | Architecture for joint detection hardware accelerator | Jun 11, 2007 | Issued |
Array
(
[id] => 4440959
[patent_doc_number] => 07971031
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-28
[patent_title] => 'Data processing system and method'
[patent_app_type] => utility
[patent_app_number] => 11/754391
[patent_app_country] => US
[patent_app_date] => 2007-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 5900
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/971/07971031.pdf
[firstpage_image] =>[orig_patent_app_number] => 11754391
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/754391 | Data processing system and method | May 28, 2007 | Issued |
Array
(
[id] => 6616128
[patent_doc_number] => 20100293342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-11-18
[patent_title] => 'DATA PROCESSING APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 12/594715
[patent_app_country] => US
[patent_app_date] => 2007-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 39816
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 17
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0293/20100293342.pdf
[firstpage_image] =>[orig_patent_app_number] => 12594715
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/594715 | Data processing apparatus with instruction encodings to enable near and far memory access modes | Apr 9, 2007 | Issued |
Array
(
[id] => 7690012
[patent_doc_number] => 20070234021
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'INTER-PORT COMMUNICATION IN A MULTI-PORT MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/694819
[patent_app_country] => US
[patent_app_date] => 2007-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4180
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0234/20070234021.pdf
[firstpage_image] =>[orig_patent_app_number] => 11694819
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/694819 | Inter-port communication in a multi-port memory device | Mar 29, 2007 | Issued |
Array
(
[id] => 5362912
[patent_doc_number] => 20090037706
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-05
[patent_title] => 'Processor Lock'
[patent_app_type] => utility
[patent_app_number] => 12/086811
[patent_app_country] => US
[patent_app_date] => 2006-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2409
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0037/20090037706.pdf
[firstpage_image] =>[orig_patent_app_number] => 12086811
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/086811 | Processor lock | Dec 20, 2006 | Issued |
Array
(
[id] => 5252124
[patent_doc_number] => 20070133580
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-14
[patent_title] => 'Communication System For Controlling Intercommunication Among A Plurality of Communication Nodes'
[patent_app_type] => utility
[patent_app_number] => 11/566307
[patent_app_country] => US
[patent_app_date] => 2006-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7199
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20070133580.pdf
[firstpage_image] =>[orig_patent_app_number] => 11566307
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/566307 | Communication system for controlling intercommunication among a plurality of communication nodes | Dec 3, 2006 | Issued |
Array
(
[id] => 7557426
[patent_doc_number] => 08069335
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-29
[patent_title] => 'Processing system and method for executing instructions'
[patent_app_type] => utility
[patent_app_number] => 12/093643
[patent_app_country] => US
[patent_app_date] => 2006-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2246
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/069/08069335.pdf
[firstpage_image] =>[orig_patent_app_number] => 12093643
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/093643 | Processing system and method for executing instructions | Nov 12, 2006 | Issued |
Array
(
[id] => 4447451
[patent_doc_number] => 07930523
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-19
[patent_title] => 'Inter-CPU data transfer device'
[patent_app_type] => utility
[patent_app_number] => 11/594853
[patent_app_country] => US
[patent_app_date] => 2006-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8098
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/930/07930523.pdf
[firstpage_image] =>[orig_patent_app_number] => 11594853
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/594853 | Inter-CPU data transfer device | Nov 8, 2006 | Issued |
Array
(
[id] => 7687819
[patent_doc_number] => 20070106879
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-10
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/593609
[patent_app_country] => US
[patent_app_date] => 2006-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8479
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0106/20070106879.pdf
[firstpage_image] =>[orig_patent_app_number] => 11593609
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/593609 | Semiconductor device | Nov 6, 2006 | Abandoned |