Daniel H. Pan

Array ( [id] => 7690012 [patent_doc_number] => 20070234021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'INTER-PORT COMMUNICATION IN A MULTI-PORT MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/694819 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4180 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20070234021.pdf [firstpage_image] =>[orig_patent_app_number] => 11694819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5362912 [patent_doc_number] => 20090037706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Processor Lock' [patent_app_type] => utility [patent_app_number] => 12/086811 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2409 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037706.pdf [firstpage_image] =>[orig_patent_app_number] => 12086811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5252124 [patent_doc_number] => 20070133580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Communication System For Controlling Intercommunication Among A Plurality of Communication Nodes' [patent_app_type] => utility [patent_app_number] => 11/566307 [patent_app_country] => US [patent_app_date] => 2006-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7199 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20070133580.pdf [firstpage_image] =>[orig_patent_app_number] => 11566307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7557426 [patent_doc_number] => 08069335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-29 [patent_title] => 'Processing system and method for executing instructions' [patent_app_type] => utility [patent_app_number] => 12/093643 [patent_app_country] => US [patent_app_date] => 2006-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2246 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/069/08069335.pdf [firstpage_image] =>[orig_patent_app_number] => 12093643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4447451 [patent_doc_number] => 07930523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Inter-CPU data transfer device' [patent_app_type] => utility [patent_app_number] => 11/594853 [patent_app_country] => US [patent_app_date] => 2006-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8098 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930523.pdf [firstpage_image] =>[orig_patent_app_number] => 11594853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7687819 [patent_doc_number] => 20070106879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/593609 [patent_app_country] => US [patent_app_date] => 2006-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8479 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20070106879.pdf [firstpage_image] =>[orig_patent_app_number] => 11593609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5232585 [patent_doc_number] => 20070294694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'Techniques for hardware-assisted multi-threaded processing' [patent_app_type] => utility [patent_app_number] => 11/454820 [patent_app_country] => US [patent_app_date] => 2006-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8876 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20070294694.pdf [firstpage_image] =>[orig_patent_app_number] => 11454820 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5418106 [patent_doc_number] => 20090043993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'Monitoring Values of Signals within an Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 12/224671 [patent_app_country] => US [patent_app_date] => 2006-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10961 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20090043993.pdf [firstpage_image] =>[orig_patent_app_number] => 12224671 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4469932 [patent_doc_number] => 07882334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Processor pipeline architecture logic state retention systems and methods' [patent_app_type] => utility [patent_app_number] => 11/276236 [patent_app_country] => US [patent_app_date] => 2006-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4389 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/882/07882334.pdf [firstpage_image] =>[orig_patent_app_number] => 11276236 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4527624 [patent_doc_number] => 07934079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Processor and its instruction issue method' [patent_app_type] => utility [patent_app_number] => 11/813991 [patent_app_country] => US [patent_app_date] => 2006-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5538 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/934/07934079.pdf [firstpage_image] =>[orig_patent_app_number] => 11813991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5867121 [patent_doc_number] => 20060101252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Information processing apparatus and context switching method' [patent_app_type] => utility [patent_app_number] => 11/229850 [patent_app_country] => US [patent_app_date] => 2005-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7146 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20060101252.pdf [firstpage_image] =>[orig_patent_app_number] => 11229850 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8010825 [patent_doc_number] => 08086830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Arithmetic processing apparatus' [patent_app_type] => utility [patent_app_number] => 11/720899 [patent_app_country] => US [patent_app_date] => 2005-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7954 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086830.pdf [firstpage_image] =>[orig_patent_app_number] => 11720899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6946653 [patent_doc_number] => 20050198471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein' [patent_app_type] => utility [patent_app_number] => 11/117509 [patent_app_country] => US [patent_app_date] => 2005-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6511 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20050198471.pdf [firstpage_image] =>[orig_patent_app_number] => 11117509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5927882 [patent_doc_number] => 20060242365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Method and apparatus for suppressing duplicative prefetches for branch target cache lines' [patent_app_type] => utility [patent_app_number] => 11/111654 [patent_app_country] => US [patent_app_date] => 2005-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3060 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20060242365.pdf [firstpage_image] =>[orig_patent_app_number] => 11111654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7052465 [patent_doc_number] => 20050188184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'System and method for handling load and/or store operations an a supperscalar microprocessor' [patent_app_type] => utility [patent_app_number] => 11/107824 [patent_app_country] => US [patent_app_date] => 2005-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10880 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20050188184.pdf [firstpage_image] =>[orig_patent_app_number] => 11107824 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7047063 [patent_doc_number] => 20050251658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Processing unit' [patent_app_type] => utility [patent_app_number] => 11/048759 [patent_app_country] => US [patent_app_date] => 2005-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5915 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20050251658.pdf [firstpage_image] =>[orig_patent_app_number] => 11048759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5668746 [patent_doc_number] => 20060174096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Methods and systems for storing branch information in an address table of a processor' [patent_app_type] => utility [patent_app_number] => 11/049014 [patent_app_country] => US [patent_app_date] => 2005-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5998 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20060174096.pdf [firstpage_image] =>[orig_patent_app_number] => 11049014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6985312 [patent_doc_number] => 20050154868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Apparatus and method for processing a sequence of jump instructions' [patent_app_type] => utility [patent_app_number] => 11/017209 [patent_app_country] => US [patent_app_date] => 2004-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8831 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20050154868.pdf [firstpage_image] =>[orig_patent_app_number] => 11017209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6973819 [patent_doc_number] => 20050038979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Method and circuits for early detection of a full queue' [patent_app_type] => utility [patent_app_number] => 10/945710 [patent_app_country] => US [patent_app_date] => 2004-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7051 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20050038979.pdf [firstpage_image] =>[orig_patent_app_number] => 10945710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7600002 [patent_doc_number] => 07386710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-10 [patent_title] => 'Methods and apparatus for scalable array processor interrupt detection and response' [patent_app_type] => utility [patent_app_number] => 10/931751 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 13769 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/386/07386710.pdf [firstpage_image] =>[orig_patent_app_number] => 10931751 [rel_patent_id] =>[rel_patent_doc_number] =>)