
Daniel H. Pan
Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )
| Most Active Art Unit | 2182 |
| Art Unit(s) | 2182, 2183, 2302, 2783, 2315, 2899 |
| Total Applications | 1471 |
| Issued Applications | 1281 |
| Pending Applications | 50 |
| Abandoned Applications | 145 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7384884
[patent_doc_number] => 20040221135
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-04
[patent_title] => 'Method for forming a single instruction multiple data massively parallel processor system on a chip'
[patent_app_type] => new
[patent_app_number] => 10/859972
[patent_app_country] => US
[patent_app_date] => 2004-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5008
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 3
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0221/20040221135.pdf
[firstpage_image] =>[orig_patent_app_number] => 10859972
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/859972 | Method for forming a single instruction multiple data massively parallel processor system on a chip | Jun 3, 2004 | Issued |
Array
(
[id] => 209655
[patent_doc_number] => RE041012
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2009-11-24
[patent_title] => 'Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor'
[patent_app_type] => reissue
[patent_app_number] => 10/860669
[patent_app_country] => US
[patent_app_date] => 2004-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 8832
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/041/RE041012.pdf
[firstpage_image] =>[orig_patent_app_number] => 10860669
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/860669 | Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor | Jun 2, 2004 | Issued |
Array
(
[id] => 806121
[patent_doc_number] => 07424594
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-09
[patent_title] => 'Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture'
[patent_app_type] => utility
[patent_app_number] => 10/859708
[patent_app_country] => US
[patent_app_date] => 2004-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 38
[patent_no_of_words] => 5814
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/424/07424594.pdf
[firstpage_image] =>[orig_patent_app_number] => 10859708
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/859708 | Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture | Jun 2, 2004 | Issued |
Array
(
[id] => 7385964
[patent_doc_number] => 20040221276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-04
[patent_title] => 'Method and computer program for data conversion in a heterogeneous communications network'
[patent_app_type] => new
[patent_app_number] => 10/860838
[patent_app_country] => US
[patent_app_date] => 2004-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3426
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 3
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0221/20040221276.pdf
[firstpage_image] =>[orig_patent_app_number] => 10860838
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/860838 | Method and computer program for data conversion in a heterogeneous communications network | Jun 2, 2004 | Abandoned |
Array
(
[id] => 7273491
[patent_doc_number] => 20040232942
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-25
[patent_title] => 'Field programmable gate array and microcontroller system-on-a-chip'
[patent_app_type] => new
[patent_app_number] => 10/821533
[patent_app_country] => US
[patent_app_date] => 2004-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 9613
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0232/20040232942.pdf
[firstpage_image] =>[orig_patent_app_number] => 10821533
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/821533 | Field programmable gate array and microcontroller system-on-a-chip | Apr 7, 2004 | Issued |
Array
(
[id] => 7418273
[patent_doc_number] => 20040177235
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-09
[patent_title] => 'Enhanced boolean processor'
[patent_app_type] => new
[patent_app_number] => 10/803690
[patent_app_country] => US
[patent_app_date] => 2004-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 38
[patent_no_of_words] => 33426
[patent_no_of_claims] => 146
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0177/20040177235.pdf
[firstpage_image] =>[orig_patent_app_number] => 10803690
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/803690 | Enhanced boolean processor | Mar 16, 2004 | Issued |
Array
(
[id] => 598585
[patent_doc_number] => 07447880
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-11-04
[patent_title] => 'Processor with internal memory configuration'
[patent_app_type] => utility
[patent_app_number] => 10/723448
[patent_app_country] => US
[patent_app_date] => 2003-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 4149
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/447/07447880.pdf
[firstpage_image] =>[orig_patent_app_number] => 10723448
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/723448 | Processor with internal memory configuration | Nov 24, 2003 | Issued |
Array
(
[id] => 947679
[patent_doc_number] => 06965987
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-15
[patent_title] => 'System and method for handling load and/or store operations in a superscalar microprocessor'
[patent_app_type] => utility
[patent_app_number] => 10/713145
[patent_app_country] => US
[patent_app_date] => 2003-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 10903
[patent_no_of_claims] => 58
[patent_no_of_ind_claims] => 42
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/965/06965987.pdf
[firstpage_image] =>[orig_patent_app_number] => 10713145
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/713145 | System and method for handling load and/or store operations in a superscalar microprocessor | Nov 16, 2003 | Issued |
Array
(
[id] => 586608
[patent_doc_number] => 07467288
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-16
[patent_title] => 'Vector register file with arbitrary vector addressing'
[patent_app_type] => utility
[patent_app_number] => 10/713502
[patent_app_country] => US
[patent_app_date] => 2003-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5931
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/467/07467288.pdf
[firstpage_image] =>[orig_patent_app_number] => 10713502
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/713502 | Vector register file with arbitrary vector addressing | Nov 14, 2003 | Issued |
Array
(
[id] => 7373960
[patent_doc_number] => 20040093482
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-13
[patent_title] => 'High-performance, superscalar-based computer system with out-of-order instruction execution'
[patent_app_type] => new
[patent_app_number] => 10/700520
[patent_app_country] => US
[patent_app_date] => 2003-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 32375
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0093/20040093482.pdf
[firstpage_image] =>[orig_patent_app_number] => 10700520
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/700520 | High-performance, superscalar-based computer system with out-of-order instruction execution | Nov 4, 2003 | Issued |
Array
(
[id] => 978757
[patent_doc_number] => 06934829
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-23
[patent_title] => 'High-performance, superscalar-based computer system with out-of-order instruction execution'
[patent_app_type] => utility
[patent_app_number] => 10/697257
[patent_app_country] => US
[patent_app_date] => 2003-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 21
[patent_no_of_words] => 32034
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/934/06934829.pdf
[firstpage_image] =>[orig_patent_app_number] => 10697257
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/697257 | High-performance, superscalar-based computer system with out-of-order instruction execution | Oct 30, 2003 | Issued |
Array
(
[id] => 582263
[patent_doc_number] => 07162610
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-09
[patent_title] => 'High-performance, superscalar-based computer system with out-of-order instruction execution'
[patent_app_type] => utility
[patent_app_number] => 10/660671
[patent_app_country] => US
[patent_app_date] => 2003-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 21
[patent_no_of_words] => 32025
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/162/07162610.pdf
[firstpage_image] =>[orig_patent_app_number] => 10660671
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/660671 | High-performance, superscalar-based computer system with out-of-order instruction execution | Sep 11, 2003 | Issued |
Array
(
[id] => 7129135
[patent_doc_number] => 20050060517
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-17
[patent_title] => 'Switching processor threads during long latencies'
[patent_app_type] => utility
[patent_app_number] => 10/661079
[patent_app_country] => US
[patent_app_date] => 2003-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2666
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0060/20050060517.pdf
[firstpage_image] =>[orig_patent_app_number] => 10661079
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/661079 | Switching processor threads during long latencies | Sep 11, 2003 | Abandoned |
Array
(
[id] => 856295
[patent_doc_number] => 07380110
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-05-27
[patent_title] => 'Branch prediction structure with branch direction entries that share branch prediction qualifier entries'
[patent_app_type] => utility
[patent_app_number] => 10/660169
[patent_app_country] => US
[patent_app_date] => 2003-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2877
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/380/07380110.pdf
[firstpage_image] =>[orig_patent_app_number] => 10660169
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/660169 | Branch prediction structure with branch direction entries that share branch prediction qualifier entries | Sep 10, 2003 | Issued |
Array
(
[id] => 7222774
[patent_doc_number] => 20050055541
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-10
[patent_title] => 'Method and apparatus for efficient utilization for prescient instruction prefetch'
[patent_app_type] => utility
[patent_app_number] => 10/658072
[patent_app_country] => US
[patent_app_date] => 2003-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 13396
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0055/20050055541.pdf
[firstpage_image] =>[orig_patent_app_number] => 10658072
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/658072 | Method and apparatus for efficient utilization for prescient instruction prefetch | Sep 7, 2003 | Issued |
Array
(
[id] => 7204966
[patent_doc_number] => 20050053012
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-10
[patent_title] => 'Data processing system having instruction specifiers for SIMD register operands and method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/657331
[patent_app_country] => US
[patent_app_date] => 2003-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 25169
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0053/20050053012.pdf
[firstpage_image] =>[orig_patent_app_number] => 10657331
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/657331 | Data processing system having instruction specifiers for SIMD register operands and method thereof | Sep 7, 2003 | Issued |
Array
(
[id] => 423676
[patent_doc_number] => 07275148
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-25
[patent_title] => 'Data processing system using multiple addressing modes for SIMD operations and method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/657797
[patent_app_country] => US
[patent_app_date] => 2003-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 35
[patent_no_of_words] => 25252
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/275/07275148.pdf
[firstpage_image] =>[orig_patent_app_number] => 10657797
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/657797 | Data processing system using multiple addressing modes for SIMD operations and method thereof | Sep 7, 2003 | Issued |
Array
(
[id] => 407198
[patent_doc_number] => 07290122
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-30
[patent_title] => 'Dataflow graph compression for power reduction in a vector processor'
[patent_app_type] => utility
[patent_app_number] => 10/652134
[patent_app_country] => US
[patent_app_date] => 2003-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2082
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/290/07290122.pdf
[firstpage_image] =>[orig_patent_app_number] => 10652134
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/652134 | Dataflow graph compression for power reduction in a vector processor | Aug 28, 2003 | Issued |
Array
(
[id] => 960013
[patent_doc_number] => 06954842
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-10-11
[patent_title] => 'Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution'
[patent_app_type] => utility
[patent_app_number] => 10/650301
[patent_app_country] => US
[patent_app_date] => 2003-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 9333
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/954/06954842.pdf
[firstpage_image] =>[orig_patent_app_number] => 10650301
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/650301 | Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution | Aug 27, 2003 | Issued |
Array
(
[id] => 7404832
[patent_doc_number] => 20040039899
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-26
[patent_title] => 'Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution'
[patent_app_type] => new
[patent_app_number] => 10/650340
[patent_app_country] => US
[patent_app_date] => 2003-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9365
[patent_no_of_claims] => 55
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0039/20040039899.pdf
[firstpage_image] =>[orig_patent_app_number] => 10650340
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/650340 | Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution | Aug 27, 2003 | Issued |