
Daniel H. Pan
Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )
| Most Active Art Unit | 2182 |
| Art Unit(s) | 2182, 2183, 2302, 2783, 2315, 2899 |
| Total Applications | 1471 |
| Issued Applications | 1281 |
| Pending Applications | 50 |
| Abandoned Applications | 145 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 548830
[patent_doc_number] => 07185177
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-27
[patent_title] => 'Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors'
[patent_app_type] => utility
[patent_app_number] => 10/648154
[patent_app_country] => US
[patent_app_date] => 2003-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 14211
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/185/07185177.pdf
[firstpage_image] =>[orig_patent_app_number] => 10648154
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/648154 | Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors | Aug 25, 2003 | Issued |
Array
(
[id] => 7404785
[patent_doc_number] => 20040039895
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-26
[patent_title] => 'Memory shared between processing threads'
[patent_app_type] => new
[patent_app_number] => 10/644337
[patent_app_country] => US
[patent_app_date] => 2003-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4592
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0039/20040039895.pdf
[firstpage_image] =>[orig_patent_app_number] => 10644337
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/644337 | Memory shared between processing threads | Aug 19, 2003 | Abandoned |
Array
(
[id] => 860407
[patent_doc_number] => 07376818
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-20
[patent_title] => 'Program translator and processor'
[patent_app_type] => utility
[patent_app_number] => 10/621440
[patent_app_country] => US
[patent_app_date] => 2003-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 35
[patent_no_of_words] => 9617
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/376/07376818.pdf
[firstpage_image] =>[orig_patent_app_number] => 10621440
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/621440 | Program translator and processor | Jul 17, 2003 | Issued |
Array
(
[id] => 7601952
[patent_doc_number] => 07237092
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-26
[patent_title] => 'Microprocessor circuit for portable data carriers and method for operating the circuit'
[patent_app_type] => utility
[patent_app_number] => 10/622981
[patent_app_country] => US
[patent_app_date] => 2003-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 4997
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/237/07237092.pdf
[firstpage_image] =>[orig_patent_app_number] => 10622981
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/622981 | Microprocessor circuit for portable data carriers and method for operating the circuit | Jul 17, 2003 | Issued |
Array
(
[id] => 7315945
[patent_doc_number] => 20040034678
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-19
[patent_title] => 'Efficient circuits for out-of-order microprocessors'
[patent_app_type] => new
[patent_app_number] => 10/608621
[patent_app_country] => US
[patent_app_date] => 2003-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 66
[patent_figures_cnt] => 66
[patent_no_of_words] => 41866
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 6
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0034/20040034678.pdf
[firstpage_image] =>[orig_patent_app_number] => 10608621
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/608621 | Efficient circuits for out-of-order microprocessors | Jun 26, 2003 | Abandoned |
Array
(
[id] => 806126
[patent_doc_number] => 07424597
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-09
[patent_title] => 'Variable reordering (Mux) instructions for parallel table lookups from registers'
[patent_app_type] => utility
[patent_app_number] => 10/403785
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3890
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/424/07424597.pdf
[firstpage_image] =>[orig_patent_app_number] => 10403785
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/403785 | Variable reordering (Mux) instructions for parallel table lookups from registers | Mar 30, 2003 | Issued |
Array
(
[id] => 7352929
[patent_doc_number] => 20040193838
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-30
[patent_title] => 'Vector instructions composed from scalar instructions'
[patent_app_type] => new
[patent_app_number] => 10/403241
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10292
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0193/20040193838.pdf
[firstpage_image] =>[orig_patent_app_number] => 10403241
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/403241 | Vector instructions composed from scalar instructions | Mar 30, 2003 | Abandoned |
Array
(
[id] => 7353046
[patent_doc_number] => 20040193855
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-30
[patent_title] => 'System and method for branch prediction access'
[patent_app_type] => new
[patent_app_number] => 10/401962
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4613
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0193/20040193855.pdf
[firstpage_image] =>[orig_patent_app_number] => 10401962
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/401962 | System and method for branch prediction access | Mar 30, 2003 | Abandoned |
Array
(
[id] => 7352924
[patent_doc_number] => 20040193837
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-30
[patent_title] => 'CPU datapaths and local memory that executes either vector or superscalar instructions'
[patent_app_type] => new
[patent_app_number] => 10/403216
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 15018
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0193/20040193837.pdf
[firstpage_image] =>[orig_patent_app_number] => 10403216
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/403216 | CPU datapaths and local memory that executes either vector or superscalar instructions | Mar 30, 2003 | Abandoned |
Array
(
[id] => 7057328
[patent_doc_number] => 20050278503
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-15
[patent_title] => 'Coprocessor bus architecture'
[patent_app_type] => utility
[patent_app_number] => 10/403428
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2966
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0278/20050278503.pdf
[firstpage_image] =>[orig_patent_app_number] => 10403428
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/403428 | Coprocessor bus architecture | Mar 30, 2003 | Abandoned |
Array
(
[id] => 6866400
[patent_doc_number] => 20030191926
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-09
[patent_title] => 'Method and apparatus for performing addressing operations in a superscalar, superpipelined processor'
[patent_app_type] => new
[patent_app_number] => 10/401170
[patent_app_country] => US
[patent_app_date] => 2003-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4037
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0191/20030191926.pdf
[firstpage_image] =>[orig_patent_app_number] => 10401170
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/401170 | Method and apparatus for performing addressing operations in a superscalar, superpipelined processor | Mar 26, 2003 | Issued |
Array
(
[id] => 534641
[patent_doc_number] => 07194602
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-20
[patent_title] => 'Data processor'
[patent_app_type] => utility
[patent_app_number] => 10/385854
[patent_app_country] => US
[patent_app_date] => 2003-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 25
[patent_no_of_words] => 17431
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/194/07194602.pdf
[firstpage_image] =>[orig_patent_app_number] => 10385854
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/385854 | Data processor | Mar 11, 2003 | Issued |
Array
(
[id] => 6831288
[patent_doc_number] => 20030182346
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-25
[patent_title] => 'Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements'
[patent_app_type] => new
[patent_app_number] => 10/375543
[patent_app_country] => US
[patent_app_date] => 2003-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 11310
[patent_no_of_claims] => 55
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0182/20030182346.pdf
[firstpage_image] =>[orig_patent_app_number] => 10375543
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/375543 | Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements | Feb 26, 2003 | Issued |
Array
(
[id] => 7706234
[patent_doc_number] => 08090930
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-03
[patent_title] => 'Method and circuits for early detection of a full queue'
[patent_app_type] => utility
[patent_app_number] => 10/356943
[patent_app_country] => US
[patent_app_date] => 2003-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 20
[patent_no_of_words] => 7055
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/090/08090930.pdf
[firstpage_image] =>[orig_patent_app_number] => 10356943
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/356943 | Method and circuits for early detection of a full queue | Jan 30, 2003 | Issued |
Array
(
[id] => 7600005
[patent_doc_number] => 07386707
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-06-10
[patent_title] => 'Processor and program execution method capable of efficient program execution'
[patent_app_type] => utility
[patent_app_number] => 10/338408
[patent_app_country] => US
[patent_app_date] => 2003-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 49
[patent_no_of_words] => 34890
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 365
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/386/07386707.pdf
[firstpage_image] =>[orig_patent_app_number] => 10338408
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/338408 | Processor and program execution method capable of efficient program execution | Jan 7, 2003 | Issued |
Array
(
[id] => 995897
[patent_doc_number] => 06918025
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-12
[patent_title] => 'IC with wait state registers'
[patent_app_type] => utility
[patent_app_number] => 10/337028
[patent_app_country] => US
[patent_app_date] => 2003-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 50
[patent_no_of_words] => 33738
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/918/06918025.pdf
[firstpage_image] =>[orig_patent_app_number] => 10337028
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/337028 | IC with wait state registers | Jan 5, 2003 | Issued |
Array
(
[id] => 7443021
[patent_doc_number] => 20040210739
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-21
[patent_title] => 'Vector signal processor'
[patent_app_type] => new
[patent_app_number] => 10/336860
[patent_app_country] => US
[patent_app_date] => 2003-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3594
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0210/20040210739.pdf
[firstpage_image] =>[orig_patent_app_number] => 10336860
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/336860 | Vector signal processor | Jan 5, 2003 | Abandoned |
Array
(
[id] => 434970
[patent_doc_number] => 07266672
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-04
[patent_title] => 'Method and apparatus for retiming in a network of multiple context processing elements'
[patent_app_type] => utility
[patent_app_number] => 10/320018
[patent_app_country] => US
[patent_app_date] => 2002-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 8825
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/266/07266672.pdf
[firstpage_image] =>[orig_patent_app_number] => 10320018
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/320018 | Method and apparatus for retiming in a network of multiple context processing elements | Dec 15, 2002 | Issued |
Array
(
[id] => 7608108
[patent_doc_number] => 07000092
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-14
[patent_title] => 'Heterogeneous multi-processor reference design'
[patent_app_type] => utility
[patent_app_number] => 10/318232
[patent_app_country] => US
[patent_app_date] => 2002-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4773
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/000/07000092.pdf
[firstpage_image] =>[orig_patent_app_number] => 10318232
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/318232 | Heterogeneous multi-processor reference design | Dec 11, 2002 | Issued |
Array
(
[id] => 7309082
[patent_doc_number] => 20040117605
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-17
[patent_title] => 'Digital processor with programmable breakpoint/watchpoint trigger generation circuit'
[patent_app_type] => new
[patent_app_number] => 10/317875
[patent_app_country] => US
[patent_app_date] => 2002-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5724
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0117/20040117605.pdf
[firstpage_image] =>[orig_patent_app_number] => 10317875
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/317875 | Digital processor with programmable breakpoint/watchpoint trigger generation circuit | Dec 10, 2002 | Issued |