Search

Daniel H. Pan

Examiner (ID: 6004, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2315, 2182, 2783, 2899, 2302, 2183
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6722397 [patent_doc_number] => 20030056087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'High-performance, superscalar-based computer system with out-of-order instruction execution' [patent_app_type] => new [patent_app_number] => 10/283106 [patent_app_country] => US [patent_app_date] => 2002-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 32340 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20030056087.pdf [firstpage_image] =>[orig_patent_app_number] => 10283106 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/283106
High-performance, superscalar-based computer system with out-of-order instruction execution Oct 29, 2002 Issued
Array ( [id] => 792699 [patent_doc_number] => 06986024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'High-performance, superscalar-based computer system with out-of-order instruction execution' [patent_app_type] => utility [patent_app_number] => 10/283177 [patent_app_country] => US [patent_app_date] => 2002-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 32031 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/986/06986024.pdf [firstpage_image] =>[orig_patent_app_number] => 10283177 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/283177
High-performance, superscalar-based computer system with out-of-order instruction execution Oct 29, 2002 Issued
Array ( [id] => 690839 [patent_doc_number] => 07080239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Loop control circuit and loop control method' [patent_app_type] => utility [patent_app_number] => 10/283310 [patent_app_country] => US [patent_app_date] => 2002-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6078 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/080/07080239.pdf [firstpage_image] =>[orig_patent_app_number] => 10283310 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/283310
Loop control circuit and loop control method Oct 29, 2002 Issued
Array ( [id] => 392845 [patent_doc_number] => 07302551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Suppression of store checking' [patent_app_type] => utility [patent_app_number] => 10/283397 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9158 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/302/07302551.pdf [firstpage_image] =>[orig_patent_app_number] => 10283397 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/283397
Suppression of store checking Oct 28, 2002 Issued
Array ( [id] => 7615395 [patent_doc_number] => 06948052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-20 [patent_title] => 'High-performance, superscalar-based computer system with out-of-order instruction execution' [patent_app_type] => utility [patent_app_number] => 10/282207 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 32016 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/948/06948052.pdf [firstpage_image] =>[orig_patent_app_number] => 10282207 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/282207
High-performance, superscalar-based computer system with out-of-order instruction execution Oct 28, 2002 Issued
Array ( [id] => 6722396 [patent_doc_number] => 20030056086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'High-performance, superscalar-based computer system with out-of-order instruction execution' [patent_app_type] => new [patent_app_number] => 10/282045 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 32342 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20030056086.pdf [firstpage_image] =>[orig_patent_app_number] => 10282045 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/282045
High-performance, superscalar-based computer system with out-of-order instruction execution Oct 28, 2002 Issued
Array ( [id] => 7234378 [patent_doc_number] => 20040073781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'Method and apparatus for token triggered multithreading' [patent_app_type] => new [patent_app_number] => 10/269245 [patent_app_country] => US [patent_app_date] => 2002-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3899 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20040073781.pdf [firstpage_image] =>[orig_patent_app_number] => 10269245 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/269245
Method and apparatus for token triggered multithreading Oct 10, 2002 Issued
Array ( [id] => 7611331 [patent_doc_number] => 06904511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Method and apparatus for register file port reduction in a multithreaded processor' [patent_app_type] => utility [patent_app_number] => 10/269373 [patent_app_country] => US [patent_app_date] => 2002-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/904/06904511.pdf [firstpage_image] =>[orig_patent_app_number] => 10269373 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/269373
Method and apparatus for register file port reduction in a multithreaded processor Oct 10, 2002 Issued
Array ( [id] => 7473996 [patent_doc_number] => 20040054875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Method and apparatus to execute an instruction with a semi-fast operation in a staggered ALU' [patent_app_type] => new [patent_app_number] => 10/243440 [patent_app_country] => US [patent_app_date] => 2002-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7503 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20040054875.pdf [firstpage_image] =>[orig_patent_app_number] => 10243440 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/243440
Method and apparatus to execute an instruction with a semi-fast operation in a staggered ALU Sep 12, 2002 Issued
Array ( [id] => 757709 [patent_doc_number] => 07024543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Synchronising pipelines in a data processing apparatus' [patent_app_type] => utility [patent_app_number] => 10/242671 [patent_app_country] => US [patent_app_date] => 2002-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8293 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/024/07024543.pdf [firstpage_image] =>[orig_patent_app_number] => 10242671 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/242671
Synchronising pipelines in a data processing apparatus Sep 12, 2002 Issued
Array ( [id] => 7360769 [patent_doc_number] => 20040049666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Method and apparatus for variable pop hardware return address stack' [patent_app_type] => new [patent_app_number] => 10/242003 [patent_app_country] => US [patent_app_date] => 2002-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4208 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20040049666.pdf [firstpage_image] =>[orig_patent_app_number] => 10242003 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/242003
Method and apparatus for variable pop hardware return address stack Sep 10, 2002 Abandoned
Array ( [id] => 7360713 [patent_doc_number] => 20040049657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Extended register space apparatus and methods for processors' [patent_app_type] => new [patent_app_number] => 10/238276 [patent_app_country] => US [patent_app_date] => 2002-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5261 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20040049657.pdf [firstpage_image] =>[orig_patent_app_number] => 10238276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/238276
Extended register space apparatus and methods for processors Sep 9, 2002 Abandoned
Array ( [id] => 7608105 [patent_doc_number] => 07000095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'Method and apparatus for clearing hazards using jump instructions' [patent_app_type] => utility [patent_app_number] => 10/238993 [patent_app_country] => US [patent_app_date] => 2002-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/000/07000095.pdf [firstpage_image] =>[orig_patent_app_number] => 10238993 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/238993
Method and apparatus for clearing hazards using jump instructions Sep 5, 2002 Issued
Array ( [id] => 599132 [patent_doc_number] => 07444495 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-28 [patent_title] => 'Processor and programmable logic computing arrangement' [patent_app_type] => utility [patent_app_number] => 10/232970 [patent_app_country] => US [patent_app_date] => 2002-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2503 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/444/07444495.pdf [firstpage_image] =>[orig_patent_app_number] => 10232970 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/232970
Processor and programmable logic computing arrangement Aug 29, 2002 Issued
Array ( [id] => 726052 [patent_doc_number] => 07051186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Selective bypassing of a multi-port register file' [patent_app_type] => utility [patent_app_number] => 10/230492 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2366 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/051/07051186.pdf [firstpage_image] =>[orig_patent_app_number] => 10230492 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230492
Selective bypassing of a multi-port register file Aug 28, 2002 Issued
Array ( [id] => 6814992 [patent_doc_number] => 20030074542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Multiprocessor system and program optimizing method' [patent_app_type] => new [patent_app_number] => 10/230199 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 6836 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074542.pdf [firstpage_image] =>[orig_patent_app_number] => 10230199 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230199
Multiprocessor system and program optimizing method Aug 28, 2002 Issued
Array ( [id] => 965686 [patent_doc_number] => 06950925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-27 [patent_title] => 'Scheduler for use in a microprocessor that supports data-speculative execution' [patent_app_type] => utility [patent_app_number] => 10/229563 [patent_app_country] => US [patent_app_date] => 2002-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9179 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/950/06950925.pdf [firstpage_image] =>[orig_patent_app_number] => 10229563 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/229563
Scheduler for use in a microprocessor that supports data-speculative execution Aug 27, 2002 Issued
Array ( [id] => 536340 [patent_doc_number] => 07191313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Microprocessor' [patent_app_type] => utility [patent_app_number] => 10/227866 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6739 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/191/07191313.pdf [firstpage_image] =>[orig_patent_app_number] => 10227866 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/227866
Microprocessor Aug 26, 2002 Issued
Array ( [id] => 904902 [patent_doc_number] => 07340585 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-04 [patent_title] => 'Method and system for fast linked processor in a system on a chip (SoC)' [patent_app_type] => utility [patent_app_number] => 10/229543 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3167 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/340/07340585.pdf [firstpage_image] =>[orig_patent_app_number] => 10229543 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/229543
Method and system for fast linked processor in a system on a chip (SoC) Aug 26, 2002 Issued
Array ( [id] => 7404865 [patent_doc_number] => 20040039902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Exception handling for single instructions with multiple data' [patent_app_type] => new [patent_app_number] => 10/229317 [patent_app_country] => US [patent_app_date] => 2002-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6322 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20040039902.pdf [firstpage_image] =>[orig_patent_app_number] => 10229317 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/229317
Exception handling for single instructions with multiple data Aug 25, 2002 Issued
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