Search

Daniel H. Pan

Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2302, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6814992 [patent_doc_number] => 20030074542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Multiprocessor system and program optimizing method' [patent_app_type] => new [patent_app_number] => 10/230199 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 6836 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074542.pdf [firstpage_image] =>[orig_patent_app_number] => 10230199 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230199
Multiprocessor system and program optimizing method Aug 28, 2002 Issued
Array ( [id] => 726052 [patent_doc_number] => 07051186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Selective bypassing of a multi-port register file' [patent_app_type] => utility [patent_app_number] => 10/230492 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2366 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/051/07051186.pdf [firstpage_image] =>[orig_patent_app_number] => 10230492 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230492
Selective bypassing of a multi-port register file Aug 28, 2002 Issued
Array ( [id] => 965686 [patent_doc_number] => 06950925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-27 [patent_title] => 'Scheduler for use in a microprocessor that supports data-speculative execution' [patent_app_type] => utility [patent_app_number] => 10/229563 [patent_app_country] => US [patent_app_date] => 2002-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9179 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/950/06950925.pdf [firstpage_image] =>[orig_patent_app_number] => 10229563 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/229563
Scheduler for use in a microprocessor that supports data-speculative execution Aug 27, 2002 Issued
Array ( [id] => 904902 [patent_doc_number] => 07340585 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-04 [patent_title] => 'Method and system for fast linked processor in a system on a chip (SoC)' [patent_app_type] => utility [patent_app_number] => 10/229543 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3167 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/340/07340585.pdf [firstpage_image] =>[orig_patent_app_number] => 10229543 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/229543
Method and system for fast linked processor in a system on a chip (SoC) Aug 26, 2002 Issued
Array ( [id] => 536340 [patent_doc_number] => 07191313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Microprocessor' [patent_app_type] => utility [patent_app_number] => 10/227866 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6739 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/191/07191313.pdf [firstpage_image] =>[orig_patent_app_number] => 10227866 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/227866
Microprocessor Aug 26, 2002 Issued
Array ( [id] => 7404865 [patent_doc_number] => 20040039902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Exception handling for single instructions with multiple data' [patent_app_type] => new [patent_app_number] => 10/229317 [patent_app_country] => US [patent_app_date] => 2002-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6322 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20040039902.pdf [firstpage_image] =>[orig_patent_app_number] => 10229317 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/229317
Exception handling for single instructions with multiple data Aug 25, 2002 Issued
Array ( [id] => 839882 [patent_doc_number] => 07395412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Apparatus and method for extending data modes in a microprocessor' [patent_app_type] => utility [patent_app_number] => 10/227008 [patent_app_country] => US [patent_app_date] => 2002-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7872 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/395/07395412.pdf [firstpage_image] =>[orig_patent_app_number] => 10227008 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/227008
Apparatus and method for extending data modes in a microprocessor Aug 21, 2002 Issued
Array ( [id] => 6741651 [patent_doc_number] => 20030159020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Non-temporal memory reference control mechanism' [patent_app_type] => new [patent_app_number] => 10/227583 [patent_app_country] => US [patent_app_date] => 2002-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8902 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20030159020.pdf [firstpage_image] =>[orig_patent_app_number] => 10227583 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/227583
Non-temporal memory reference control mechanism Aug 21, 2002 Issued
Array ( [id] => 6707735 [patent_doc_number] => 20030154469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Apparatus and method for improved execution of a software pipeline loop procedure in a digital signal processor' [patent_app_type] => new [patent_app_number] => 10/225036 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10932 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20030154469.pdf [firstpage_image] =>[orig_patent_app_number] => 10225036 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/225036
Apparatus and method for improved execution of a software pipeline loop procedure in a digital signal processor Aug 20, 2002 Abandoned
Array ( [id] => 792710 [patent_doc_number] => 06986029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein' [patent_app_type] => utility [patent_app_number] => 10/201249 [patent_app_country] => US [patent_app_date] => 2002-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 6515 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/986/06986029.pdf [firstpage_image] =>[orig_patent_app_number] => 10201249 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/201249
Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein Jul 23, 2002 Issued
Array ( [id] => 6265438 [patent_doc_number] => 20020188829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'System and method for handling load and/or store operations in a superscalar microprocessor' [patent_app_type] => new [patent_app_number] => 10/190703 [patent_app_country] => US [patent_app_date] => 2002-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10961 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20020188829.pdf [firstpage_image] =>[orig_patent_app_number] => 10190703 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190703
System and method for handling load and/or store operations in a superscalar microprocessor Jul 8, 2002 Issued
10/070035 Branch instructions in a multithreaded parallel processing system Jul 2, 2002 Abandoned
Array ( [id] => 6810400 [patent_doc_number] => 20030200339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Communications system using rings architecture' [patent_app_type] => new [patent_app_number] => 10/064336 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 65 [patent_no_of_words] => 75042 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20030200339.pdf [firstpage_image] =>[orig_patent_app_number] => 10064336 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/064336
Communications system using rings architecture Jul 1, 2002 Abandoned
Array ( [id] => 7678260 [patent_doc_number] => 20030196076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-16 [patent_title] => 'Communications system using rings architecture' [patent_app_type] => new [patent_app_number] => 10/064338 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 65 [patent_no_of_words] => 74925 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20030196076.pdf [firstpage_image] =>[orig_patent_app_number] => 10064338 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/064338
Communications system using rings architecture Jul 1, 2002 Abandoned
Array ( [id] => 7608103 [patent_doc_number] => 07000097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'System and method for handling load and/or store operations in a superscalar microprocessor' [patent_app_type] => utility [patent_app_number] => 10/185007 [patent_app_country] => US [patent_app_date] => 2002-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10882 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/000/07000097.pdf [firstpage_image] =>[orig_patent_app_number] => 10185007 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185007
System and method for handling load and/or store operations in a superscalar microprocessor Jun 30, 2002 Issued
Array ( [id] => 7445395 [patent_doc_number] => 20040003208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Virtual register set expanding processor internal storage' [patent_app_type] => new [patent_app_number] => 10/184333 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5090 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20040003208.pdf [firstpage_image] =>[orig_patent_app_number] => 10184333 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/184333
Virtual register set expanding processor internal storage Jun 27, 2002 Issued
Array ( [id] => 7445458 [patent_doc_number] => 20040003213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Method for reducing the latency of a branch target calculation by linking the branch target address cache with the call-return stack' [patent_app_type] => new [patent_app_number] => 10/186935 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2587 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20040003213.pdf [firstpage_image] =>[orig_patent_app_number] => 10186935 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/186935
Method for reducing the latency of a branch target calculation by linking the branch target address cache with the call-return stack Jun 27, 2002 Abandoned
Array ( [id] => 958154 [patent_doc_number] => 06957326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-18 [patent_title] => 'Methods and apparatuses for executing threads' [patent_app_type] => utility [patent_app_number] => 10/185210 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 6137 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/957/06957326.pdf [firstpage_image] =>[orig_patent_app_number] => 10185210 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185210
Methods and apparatuses for executing threads Jun 26, 2002 Issued
Array ( [id] => 6265432 [patent_doc_number] => 20020188827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Opcode numbering for meta-data encoding' [patent_app_type] => new [patent_app_number] => 10/159300 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4698 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20020188827.pdf [firstpage_image] =>[orig_patent_app_number] => 10159300 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/159300
Opcode numbering for meta-data encoding May 30, 2002 Abandoned
Array ( [id] => 7608110 [patent_doc_number] => 07000090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'Center focused single instruction multiple data (SIMD) array system' [patent_app_type] => utility [patent_app_number] => 10/159763 [patent_app_country] => US [patent_app_date] => 2002-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2650 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/000/07000090.pdf [firstpage_image] =>[orig_patent_app_number] => 10159763 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/159763
Center focused single instruction multiple data (SIMD) array system May 29, 2002 Issued
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