Search

Daniel H. Pan

Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2302, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5910548 [patent_doc_number] => 20020144084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Processor for executing highly efficient VLIW' [patent_app_type] => new [patent_app_number] => 10/155672 [patent_app_country] => US [patent_app_date] => 2002-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10309 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20020144084.pdf [firstpage_image] =>[orig_patent_app_number] => 10155672 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/155672
Processor for executing highly efficient VLIW May 23, 2002 Issued
Array ( [id] => 6665379 [patent_doc_number] => 20030204706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Vector floating point unit' [patent_app_type] => new [patent_app_number] => 10/131359 [patent_app_country] => US [patent_app_date] => 2002-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6479 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20030204706.pdf [firstpage_image] =>[orig_patent_app_number] => 10131359 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/131359
Vector floating point unit Apr 23, 2002 Issued
Array ( [id] => 598605 [patent_doc_number] => 07447886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'System for expanded instruction encoding and method thereof' [patent_app_type] => utility [patent_app_number] => 10/127087 [patent_app_country] => US [patent_app_date] => 2002-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 36 [patent_no_of_words] => 25330 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/447/07447886.pdf [firstpage_image] =>[orig_patent_app_number] => 10127087 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/127087
System for expanded instruction encoding and method thereof Apr 21, 2002 Issued
Array ( [id] => 526898 [patent_doc_number] => 07200738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'Reducing data hazards in pipelined processors to provide high processor utilization' [patent_app_type] => utility [patent_app_number] => 10/125331 [patent_app_country] => US [patent_app_date] => 2002-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7772 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/200/07200738.pdf [firstpage_image] =>[orig_patent_app_number] => 10125331 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/125331
Reducing data hazards in pipelined processors to provide high processor utilization Apr 17, 2002 Issued
Array ( [id] => 7206811 [patent_doc_number] => 20050166038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'High-performance hybrid processor with configurable execution units' [patent_app_type] => utility [patent_app_number] => 10/120849 [patent_app_country] => US [patent_app_date] => 2002-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7109 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20050166038.pdf [firstpage_image] =>[orig_patent_app_number] => 10120849 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/120849
High-performance hybrid processor with configurable execution units Apr 9, 2002 Issued
Array ( [id] => 1177665 [patent_doc_number] => 06760831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution' [patent_app_type] => B2 [patent_app_number] => 10/114652 [patent_app_country] => US [patent_app_date] => 2002-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760831.pdf [firstpage_image] =>[orig_patent_app_number] => 10114652 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/114652
Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution Mar 31, 2002 Issued
Array ( [id] => 1129660 [patent_doc_number] => 06795909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'Methods and apparatus for ManArray PE-PE switch control' [patent_app_type] => B2 [patent_app_number] => 10/114646 [patent_app_country] => US [patent_app_date] => 2002-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 46 [patent_no_of_words] => 9298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/795/06795909.pdf [firstpage_image] =>[orig_patent_app_number] => 10114646 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/114646
Methods and apparatus for ManArray PE-PE switch control Mar 31, 2002 Issued
Array ( [id] => 599971 [patent_doc_number] => 07441104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'Parallel subword instructions with distributed results' [patent_app_type] => utility [patent_app_number] => 10/112783 [patent_app_country] => US [patent_app_date] => 2002-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3911 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/441/07441104.pdf [firstpage_image] =>[orig_patent_app_number] => 10112783 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/112783
Parallel subword instructions with distributed results Mar 29, 2002 Issued
Array ( [id] => 7613834 [patent_doc_number] => 06898697 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-24 [patent_title] => 'Efficient method for mode change detection and synchronization' [patent_app_type] => utility [patent_app_number] => 10/113387 [patent_app_country] => US [patent_app_date] => 2002-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 19586 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898697.pdf [firstpage_image] =>[orig_patent_app_number] => 10113387 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/113387
Efficient method for mode change detection and synchronization Mar 28, 2002 Issued
Array ( [id] => 596429 [patent_doc_number] => 07454601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'N-wide add-compare-select instruction' [patent_app_type] => utility [patent_app_number] => 10/107259 [patent_app_country] => US [patent_app_date] => 2002-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4622 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/454/07454601.pdf [firstpage_image] =>[orig_patent_app_number] => 10107259 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/107259
N-wide add-compare-select instruction Mar 27, 2002 Issued
Array ( [id] => 6732091 [patent_doc_number] => 20030188281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Maximal tile generation technique and associated methods for designing and manufacturing VLSI circuits' [patent_app_type] => new [patent_app_number] => 10/109125 [patent_app_country] => US [patent_app_date] => 2002-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7505 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20030188281.pdf [firstpage_image] =>[orig_patent_app_number] => 10109125 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/109125
Maximal tile generation technique and associated methods for designing and manufacturing VLSI circuits Mar 27, 2002 Issued
Array ( [id] => 6731953 [patent_doc_number] => 20030188143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => '2N- way MAX/MIN instructions using N-stage 2- way MAX/MIN blocks' [patent_app_type] => new [patent_app_number] => 10/107261 [patent_app_country] => US [patent_app_date] => 2002-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10550 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20030188143.pdf [firstpage_image] =>[orig_patent_app_number] => 10107261 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/107261
2N- way MAX/MIN instructions using N-stage 2- way MAX/MIN blocks Mar 27, 2002 Abandoned
Array ( [id] => 6731949 [patent_doc_number] => 20030188139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Flexible demand-based resource allocation for multiple requestors in a simultaneous multi-threaded CPU' [patent_app_type] => new [patent_app_number] => 10/109255 [patent_app_country] => US [patent_app_date] => 2002-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4335 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20030188139.pdf [firstpage_image] =>[orig_patent_app_number] => 10109255 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/109255
Flexible demand-based resource allocation for multiple requestors in a simultaneous multi-threaded CPU Mar 27, 2002 Issued
Array ( [id] => 6831480 [patent_doc_number] => 20030182538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Method and system for managing registers' [patent_app_type] => new [patent_app_number] => 10/103181 [patent_app_country] => US [patent_app_date] => 2002-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6338 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20030182538.pdf [firstpage_image] =>[orig_patent_app_number] => 10103181 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/103181
Method and system for managing registers Mar 19, 2002 Issued
Array ( [id] => 6689778 [patent_doc_number] => 20030033504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein' [patent_app_type] => new [patent_app_number] => 10/101480 [patent_app_country] => US [patent_app_date] => 2002-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6564 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20030033504.pdf [firstpage_image] =>[orig_patent_app_number] => 10101480 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/101480
Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein Mar 19, 2002 Issued
Array ( [id] => 6385833 [patent_doc_number] => 20020120434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Computer system having software interrupt (INTn) instructions selectively operating in a virtual mode' [patent_app_type] => new [patent_app_number] => 10/094498 [patent_app_country] => US [patent_app_date] => 2002-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3156 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20020120434.pdf [firstpage_image] =>[orig_patent_app_number] => 10094498 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/094498
Computer system and method for executing interrupt instructions in two operating modes Mar 6, 2002 Issued
Array ( [id] => 6425077 [patent_doc_number] => 20020184475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Boolean processor' [patent_app_type] => new [patent_app_number] => 10/075917 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15358 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184475.pdf [firstpage_image] =>[orig_patent_app_number] => 10075917 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/075917
Boolean processor Feb 12, 2002 Issued
Array ( [id] => 684740 [patent_doc_number] => 07085913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Hub/router for communication between cores using cartesian coordinates' [patent_app_type] => utility [patent_app_number] => 09/683778 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5494 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/085/07085913.pdf [firstpage_image] =>[orig_patent_app_number] => 09683778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/683778
Hub/router for communication between cores using cartesian coordinates Feb 12, 2002 Issued
Array ( [id] => 6707629 [patent_doc_number] => 20030154363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Stacked register aliasing in data hazard detection to reduce circuit' [patent_app_type] => new [patent_app_number] => 10/074061 [patent_app_country] => US [patent_app_date] => 2002-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2534 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20030154363.pdf [firstpage_image] =>[orig_patent_app_number] => 10074061 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/074061
Stacked register aliasing in data hazard detection to reduce circuit Feb 10, 2002 Abandoned
Array ( [id] => 1184794 [patent_doc_number] => 06748516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-08 [patent_title] => 'Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously' [patent_app_type] => B2 [patent_app_number] => 10/059698 [patent_app_country] => US [patent_app_date] => 2002-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 17171 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/748/06748516.pdf [firstpage_image] =>[orig_patent_app_number] => 10059698 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/059698
Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously Jan 28, 2002 Issued
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