Search

Daniel H. Pan

Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2302, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6561321 [patent_doc_number] => 20020138710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control' [patent_app_type] => new [patent_app_number] => 09/876189 [patent_app_country] => US [patent_app_date] => 2001-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 16931 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20020138710.pdf [firstpage_image] =>[orig_patent_app_number] => 09876189 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/876189
Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control Jun 4, 2001 Issued
Array ( [id] => 6426084 [patent_doc_number] => 20020184566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Register pointer trap' [patent_app_type] => new [patent_app_number] => 09/870446 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3786 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184566.pdf [firstpage_image] =>[orig_patent_app_number] => 09870446 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870446
Register pointer trap May 31, 2001 Abandoned
Array ( [id] => 937587 [patent_doc_number] => 06976158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-13 [patent_title] => 'Repeat instruction with interrupt' [patent_app_type] => utility [patent_app_number] => 09/870451 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6182 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/976/06976158.pdf [firstpage_image] =>[orig_patent_app_number] => 09870451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870451
Repeat instruction with interrupt May 31, 2001 Issued
Array ( [id] => 792705 [patent_doc_number] => 06986027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Universal load address/value prediction using stride-based pattern history and last-value prediction in a two-level table scheme' [patent_app_type] => utility [patent_app_number] => 09/864590 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5020 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/986/06986027.pdf [firstpage_image] =>[orig_patent_app_number] => 09864590 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864590
Universal load address/value prediction using stride-based pattern history and last-value prediction in a two-level table scheme May 23, 2001 Issued
Array ( [id] => 898000 [patent_doc_number] => 07346760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Data processing apparatus of high speed process using memory of low speed and low power consumption' [patent_app_type] => utility [patent_app_number] => 09/855594 [patent_app_country] => US [patent_app_date] => 2001-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 40 [patent_no_of_words] => 8345 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/346/07346760.pdf [firstpage_image] =>[orig_patent_app_number] => 09855594 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/855594
Data processing apparatus of high speed process using memory of low speed and low power consumption May 15, 2001 Issued
Array ( [id] => 806128 [patent_doc_number] => 07424598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-09 [patent_title] => 'Data processor' [patent_app_type] => utility [patent_app_number] => 09/853769 [patent_app_country] => US [patent_app_date] => 2001-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 39 [patent_no_of_words] => 7597 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/424/07424598.pdf [firstpage_image] =>[orig_patent_app_number] => 09853769 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/853769
Data processor May 13, 2001 Issued
Array ( [id] => 1289230 [patent_doc_number] => 06647485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'High-performance, superscalar-based computer system with out-of-order instruction execution' [patent_app_type] => B2 [patent_app_number] => 09/852293 [patent_app_country] => US [patent_app_date] => 2001-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 32003 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647485.pdf [firstpage_image] =>[orig_patent_app_number] => 09852293 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/852293
High-performance, superscalar-based computer system with out-of-order instruction execution May 9, 2001 Issued
Array ( [id] => 5953012 [patent_doc_number] => 20020007451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'Central processing unit for easily testing and debugging programs' [patent_app_type] => new [patent_app_number] => 09/841875 [patent_app_country] => US [patent_app_date] => 2001-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6451 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20020007451.pdf [firstpage_image] =>[orig_patent_app_number] => 09841875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/841875
Central processing unit for easily testing and debugging programs Apr 25, 2001 Issued
Array ( [id] => 1161667 [patent_doc_number] => 06775764 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Search function for data lookup' [patent_app_type] => B1 [patent_app_number] => 09/841271 [patent_app_country] => US [patent_app_date] => 2001-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4048 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775764.pdf [firstpage_image] =>[orig_patent_app_number] => 09841271 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/841271
Search function for data lookup Apr 23, 2001 Issued
Array ( [id] => 6181389 [patent_doc_number] => 20020156994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Coprocessor architecture for control processors using synchronous logic' [patent_app_type] => new [patent_app_number] => 09/841536 [patent_app_country] => US [patent_app_date] => 2001-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4786 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20020156994.pdf [firstpage_image] =>[orig_patent_app_number] => 09841536 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/841536
Coprocessor architecture for control processors using synchronous logic Apr 23, 2001 Pending
Array ( [id] => 6171802 [patent_doc_number] => 20020154119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Apparatus and method for performing branch processing according to a user indicated selection from displayed graphics' [patent_app_type] => new [patent_app_number] => 09/841653 [patent_app_country] => US [patent_app_date] => 2001-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3531 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20020154119.pdf [firstpage_image] =>[orig_patent_app_number] => 09841653 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/841653
Apparatus and method for performing branch processing according to a user indicated selection from displayed graphics Apr 23, 2001 Abandoned
Array ( [id] => 6988716 [patent_doc_number] => 20010037445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Cycle count replication in a simultaneous and redundantly threaded processor' [patent_app_type] => new [patent_app_number] => 09/839459 [patent_app_country] => US [patent_app_date] => 2001-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6035 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20010037445.pdf [firstpage_image] =>[orig_patent_app_number] => 09839459 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/839459
Cycle count replication in a simultaneous and redundantly threaded processor Apr 18, 2001 Issued
Array ( [id] => 645569 [patent_doc_number] => 07124280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Execution control apparatus of data driven information processor for instruction inputs' [patent_app_type] => utility [patent_app_number] => 09/833653 [patent_app_country] => US [patent_app_date] => 2001-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 6854 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124280.pdf [firstpage_image] =>[orig_patent_app_number] => 09833653 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/833653
Execution control apparatus of data driven information processor for instruction inputs Apr 12, 2001 Issued
09/806490 Microprocessor system for executing translated virtual machine bytecodes Apr 11, 2001 Abandoned
Array ( [id] => 7628167 [patent_doc_number] => 06820194 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Method for reducing power when fetching instructions in a processor and related apparatus' [patent_app_type] => B1 [patent_app_number] => 09/829823 [patent_app_country] => US [patent_app_date] => 2001-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9865 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/820/06820194.pdf [firstpage_image] =>[orig_patent_app_number] => 09829823 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/829823
Method for reducing power when fetching instructions in a processor and related apparatus Apr 9, 2001 Issued
Array ( [id] => 1197019 [patent_doc_number] => 06732258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'IP relative addressing' [patent_app_type] => B1 [patent_app_number] => 09/824899 [patent_app_country] => US [patent_app_date] => 2001-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 14396 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732258.pdf [firstpage_image] =>[orig_patent_app_number] => 09824899 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/824899
IP relative addressing Apr 1, 2001 Issued
Array ( [id] => 1037154 [patent_doc_number] => 06877084 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-05 [patent_title] => 'Central processing unit (CPU) accessing an extended register set in an extended register mode' [patent_app_type] => utility [patent_app_number] => 09/824863 [patent_app_country] => US [patent_app_date] => 2001-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7534 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/877/06877084.pdf [firstpage_image] =>[orig_patent_app_number] => 09824863 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/824863
Central processing unit (CPU) accessing an extended register set in an extended register mode Apr 1, 2001 Issued
Array ( [id] => 5910560 [patent_doc_number] => 20020144096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Retiring early-completion instructions to improve computer operation throughput' [patent_app_type] => new [patent_app_number] => 09/823596 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4781 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20020144096.pdf [firstpage_image] =>[orig_patent_app_number] => 09823596 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/823596
Retiring early-completion instructions to improve computer operation throughput Mar 29, 2001 Issued
Array ( [id] => 6561390 [patent_doc_number] => 20020138715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Microprocessor executing data transfer between memory and register and data transfer between registers in response to single push/pop instruction' [patent_app_type] => new [patent_app_number] => 09/819990 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8158 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20020138715.pdf [firstpage_image] =>[orig_patent_app_number] => 09819990 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/819990
Microprocessor executing data transfer between memory and register and data transfer between registers in response to single push/pop instruction Mar 28, 2001 Abandoned
Array ( [id] => 6561413 [patent_doc_number] => 20020138716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements' [patent_app_type] => new [patent_app_number] => 09/815122 [patent_app_country] => US [patent_app_date] => 2001-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8353 [patent_no_of_claims] => 74 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20020138716.pdf [firstpage_image] =>[orig_patent_app_number] => 09815122 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/815122
Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements Mar 21, 2001 Issued
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