Daniel H. Pan

Array ( [id] => 17076664 [patent_doc_number] => 11113062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Inserting predefined pad values into a stream of vectors [patent_app_type] => utility [patent_app_number] => 16/420480 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 49 [patent_no_of_words] => 36684 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420480 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16844715 [patent_doc_number] => 11016801 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-25 [patent_title] => Architecture to support color scheme-based synchronization for machine learning [patent_app_type] => utility [patent_app_number] => 16/420055 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4792 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16652596 [patent_doc_number] => 10929779 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-23 [patent_title] => Architecture to support synchronization between core and inference engine for machine learning [patent_app_type] => utility [patent_app_number] => 16/420092 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4792 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16652595 [patent_doc_number] => 10929778 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-23 [patent_title] => Address interleaving for machine learning [patent_app_type] => utility [patent_app_number] => 16/420078 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2986 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16323035 [patent_doc_number] => 10783000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Associating working sets and threads [patent_app_type] => utility [patent_app_number] => 16/407043 [patent_app_country] => US [patent_app_date] => 2019-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 31 [patent_no_of_words] => 40163 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16407043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16787965 [patent_doc_number] => 10990398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Mechanism for interrupting and resuming execution on an unprotected pipeline processor [patent_app_type] => utility [patent_app_number] => 16/384434 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 11211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16384434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16927030 [patent_doc_number] => 11048513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Entering protected pipeline mode with clearing [patent_app_type] => utility [patent_app_number] => 16/384537 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 11223 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16384537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17308988 [patent_doc_number] => 11210098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Variable latency instructions [patent_app_type] => utility [patent_app_number] => 16/384328 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 12729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16384328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16879849 [patent_doc_number] => 11029997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Entering protected pipeline mode without annulling pending instructions [patent_app_type] => utility [patent_app_number] => 16/384484 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 11363 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16384484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16263225 [patent_doc_number] => 10754657 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-25 [patent_title] => Computer vision processing in hardware data paths [patent_app_type] => utility [patent_app_number] => 16/381388 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16381388 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15474867 [patent_doc_number] => 10553316 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-02-04 [patent_title] => Systems and methods for generating alimentary instruction sets based on vibrant constitutional guidance [patent_app_type] => utility [patent_app_number] => 16/375303 [patent_app_country] => US [patent_app_date] => 2019-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 35177 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16375303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14935015 [patent_doc_number] => 20190303145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => Efficient Loop Execution for a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric [patent_app_type] => utility [patent_app_number] => 16/371051 [patent_app_country] => US [patent_app_date] => 2019-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16371051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16818625 [patent_doc_number] => 11003451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Execution control of a multi-threaded, self-scheduling reconfigurable computing fabric [patent_app_type] => utility [patent_app_number] => 16/371055 [patent_app_country] => US [patent_app_date] => 2019-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 29 [patent_no_of_words] => 31691 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16371055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14935013 [patent_doc_number] => 20190303144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => Backpressure Control Using a Stop Signal for a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric [patent_app_type] => utility [patent_app_number] => 16/371045 [patent_app_country] => US [patent_app_date] => 2019-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31694 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16371045 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14935017 [patent_doc_number] => 20190303146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => Multiple Types of Thread Identifiers for a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric [patent_app_type] => utility [patent_app_number] => 16/371054 [patent_app_country] => US [patent_app_date] => 2019-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16371054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17091598 [patent_doc_number] => 11119787 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-14 [patent_title] => Non-intrusive hardware profiling [patent_app_type] => utility [patent_app_number] => 16/368263 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 17395 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16368263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16737603 [patent_doc_number] => 10963255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Implied fence on stream open [patent_app_type] => utility [patent_app_number] => 16/297824 [patent_app_country] => US [patent_app_date] => 2019-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9879 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16297824 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16446795 [patent_doc_number] => 10838724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Accessing data in multi-dimensional tensors [patent_app_type] => utility [patent_app_number] => 16/298535 [patent_app_country] => US [patent_app_date] => 2019-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16298535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14689059 [patent_doc_number] => 20190243645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => VECTOR PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 16/291176 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291176 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14506325 [patent_doc_number] => 20190196817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => Mechanism to Queue Multiple Streams to Run on Streaming Engine [patent_app_type] => utility [patent_app_number] => 16/290872 [patent_app_country] => US [patent_app_date] => 2019-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16290872 [rel_patent_id] =>[rel_patent_doc_number] =>)