Search

Daniel H. Pan

Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2302, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1116644 [patent_doc_number] => 06804770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-12 [patent_title] => 'Method and apparatus for using past history to avoid flush conditions in a microprocessor' [patent_app_type] => B2 [patent_app_number] => 09/815553 [patent_app_country] => US [patent_app_date] => 2001-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2402 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/804/06804770.pdf [firstpage_image] =>[orig_patent_app_number] => 09815553 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/815553
Method and apparatus for using past history to avoid flush conditions in a microprocessor Mar 21, 2001 Issued
Array ( [id] => 680081 [patent_doc_number] => 07089405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Index-based scoreboarding system and method' [patent_app_type] => utility [patent_app_number] => 09/813498 [patent_app_country] => US [patent_app_date] => 2001-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5912 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/089/07089405.pdf [firstpage_image] =>[orig_patent_app_number] => 09813498 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/813498
Index-based scoreboarding system and method Mar 20, 2001 Issued
Array ( [id] => 726069 [patent_doc_number] => 07051194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Self-synchronous transfer control circuit and data driven information processing device using the same' [patent_app_type] => utility [patent_app_number] => 09/813090 [patent_app_country] => US [patent_app_date] => 2001-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 49 [patent_no_of_words] => 10863 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/051/07051194.pdf [firstpage_image] =>[orig_patent_app_number] => 09813090 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/813090
Self-synchronous transfer control circuit and data driven information processing device using the same Mar 20, 2001 Issued
Array ( [id] => 1116654 [patent_doc_number] => 06804772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-12 [patent_title] => 'Dynamic field patchable microarchitecture' [patent_app_type] => B2 [patent_app_number] => 09/815098 [patent_app_country] => US [patent_app_date] => 2001-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 4746 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/804/06804772.pdf [firstpage_image] =>[orig_patent_app_number] => 09815098 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/815098
Dynamic field patchable microarchitecture Mar 20, 2001 Issued
Array ( [id] => 6988675 [patent_doc_number] => 20010037427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Information processing apparatus with parallel accumulation capability' [patent_app_type] => new [patent_app_number] => 09/802943 [patent_app_country] => US [patent_app_date] => 2001-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8460 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20010037427.pdf [firstpage_image] =>[orig_patent_app_number] => 09802943 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/802943
Information processing apparatus with parallel accumulation capability Mar 11, 2001 Issued
Array ( [id] => 1348082 [patent_doc_number] => 06598147 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Data processing device and method' [patent_app_type] => B1 [patent_app_number] => 09/674409 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 12411 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598147.pdf [firstpage_image] =>[orig_patent_app_number] => 09674409 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/674409
Data processing device and method Feb 27, 2001 Issued
Array ( [id] => 6425107 [patent_doc_number] => 20020184477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Apparatus and method for facilitating debugging of sequences of processing instructions' [patent_app_type] => new [patent_app_number] => 09/792643 [patent_app_country] => US [patent_app_date] => 2001-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 17152 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184477.pdf [firstpage_image] =>[orig_patent_app_number] => 09792643 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/792643
Apparatus and method for facilitating debugging of sequences of processing instructions using context identifier comparison Feb 25, 2001 Issued
Array ( [id] => 1357231 [patent_doc_number] => 06591357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-08 [patent_title] => 'Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements' [patent_app_type] => B2 [patent_app_number] => 09/795672 [patent_app_country] => US [patent_app_date] => 2001-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 11201 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591357.pdf [firstpage_image] =>[orig_patent_app_number] => 09795672 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/795672
Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements Feb 25, 2001 Issued
Array ( [id] => 680086 [patent_doc_number] => 07089407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Packet processing device processing input packet data in a packet routing device' [patent_app_type] => utility [patent_app_number] => 09/792304 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8807 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/089/07089407.pdf [firstpage_image] =>[orig_patent_app_number] => 09792304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/792304
Packet processing device processing input packet data in a packet routing device Feb 22, 2001 Issued
Array ( [id] => 1604506 [patent_doc_number] => 06434692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'High-throughput interface between a system memory controller and a peripheral device' [patent_app_type] => B1 [patent_app_number] => 09/792496 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 8863 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434692.pdf [firstpage_image] =>[orig_patent_app_number] => 09792496 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/792496
High-throughput interface between a system memory controller and a peripheral device Feb 22, 2001 Issued
Array ( [id] => 1183630 [patent_doc_number] => 06751725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Methods and apparatuses to clear state for operation of a stack' [patent_app_type] => B2 [patent_app_number] => 09/785303 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 27 [patent_no_of_words] => 32423 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751725.pdf [firstpage_image] =>[orig_patent_app_number] => 09785303 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/785303
Methods and apparatuses to clear state for operation of a stack Feb 15, 2001 Issued
Array ( [id] => 7638595 [patent_doc_number] => 06397326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Method and circuit for preloading prediction circuits in microprocessors' [patent_app_type] => B1 [patent_app_number] => 09/788027 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6789 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397326.pdf [firstpage_image] =>[orig_patent_app_number] => 09788027 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/788027
Method and circuit for preloading prediction circuits in microprocessors Feb 15, 2001 Issued
Array ( [id] => 7118681 [patent_doc_number] => 20010001874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-24 [patent_title] => 'Data processor' [patent_app_type] => new-utility [patent_app_number] => 09/761177 [patent_app_country] => US [patent_app_date] => 2001-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 17596 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001874.pdf [firstpage_image] =>[orig_patent_app_number] => 09761177 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/761177
Data processor Jan 17, 2001 Issued
Array ( [id] => 1052610 [patent_doc_number] => 06862676 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-01 [patent_title] => 'Superscalar processor having content addressable memory structures for determining dependencies' [patent_app_type] => utility [patent_app_number] => 09/761494 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5162 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/862/06862676.pdf [firstpage_image] =>[orig_patent_app_number] => 09761494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/761494
Superscalar processor having content addressable memory structures for determining dependencies Jan 15, 2001 Issued
Array ( [id] => 6668710 [patent_doc_number] => 20030113693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Simple programmable computer' [patent_app_type] => new [patent_app_number] => 09/757273 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2497 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20030113693.pdf [firstpage_image] =>[orig_patent_app_number] => 09757273 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/757273
Simple programmable computer Jan 9, 2001 Abandoned
Array ( [id] => 832554 [patent_doc_number] => 07401211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-15 [patent_title] => 'Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor' [patent_app_type] => utility [patent_app_number] => 09/751762 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1674 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/401/07401211.pdf [firstpage_image] =>[orig_patent_app_number] => 09751762 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751762
Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor Dec 28, 2000 Issued
Array ( [id] => 5830496 [patent_doc_number] => 20020069350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Apparatus and method for executing a block data transfer instruction inside processor' [patent_app_type] => new [patent_app_number] => 09/750465 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2493 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20020069350.pdf [firstpage_image] =>[orig_patent_app_number] => 09750465 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750465
Apparatus and method for executing an instruction with a register bit mask for transferring data between a plurality of registers and memory inside a processor Dec 27, 2000 Issued
Array ( [id] => 126737 [patent_doc_number] => 07711925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-04 [patent_title] => 'Information-processing device with transaction processor for executing subset of instruction set where if transaction processor cannot efficiently execute the instruction it is sent to general-purpose processor via interrupt' [patent_app_type] => utility [patent_app_number] => 09/746068 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6682 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/711/07711925.pdf [firstpage_image] =>[orig_patent_app_number] => 09746068 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/746068
Information-processing device with transaction processor for executing subset of instruction set where if transaction processor cannot efficiently execute the instruction it is sent to general-purpose processor via interrupt Dec 25, 2000 Issued
Array ( [id] => 6901896 [patent_doc_number] => 20010023479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'Information processing unit, and exception processing method for specific application-purpose operation instruction' [patent_app_type] => new [patent_app_number] => 09/741802 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 24936 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20010023479.pdf [firstpage_image] =>[orig_patent_app_number] => 09741802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741802
Information processing unit, and exception processing method for specific application-purpose operation instruction Dec 21, 2000 Issued
Array ( [id] => 1033762 [patent_doc_number] => 06880074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-12 [patent_title] => 'In-line code suppression' [patent_app_type] => utility [patent_app_number] => 09/681077 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2371 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/880/06880074.pdf [firstpage_image] =>[orig_patent_app_number] => 09681077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/681077
In-line code suppression Dec 21, 2000 Issued
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