Daniel H. Pan

Array ( [id] => 6886997 [patent_doc_number] => 20010020266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-06 [patent_title] => 'Packet processor' [patent_app_type] => new [patent_app_number] => 09/742939 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11317 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20010020266.pdf [firstpage_image] =>[orig_patent_app_number] => 09742939 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 662979 [patent_doc_number] => 07107434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'System, method and apparatus for allocating hardware resources using pseudorandom sequences' [patent_app_type] => utility [patent_app_number] => 09/741616 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5648 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/107/07107434.pdf [firstpage_image] =>[orig_patent_app_number] => 09741616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 626410 [patent_doc_number] => 07139903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Conflict free parallel read access to a bank interleaved branch predictor in a processor' [patent_app_type] => utility [patent_app_number] => 09/740419 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139903.pdf [firstpage_image] =>[orig_patent_app_number] => 09740419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1092896 [patent_doc_number] => 06829701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-07 [patent_title] => 'Watchpoint engine for a pipelined processor' [patent_app_type] => B2 [patent_app_number] => 09/739092 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5454 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/829/06829701.pdf [firstpage_image] =>[orig_patent_app_number] => 09739092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1030615 [patent_doc_number] => 06883087 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-19 [patent_title] => 'Processing of binary data for compression' [patent_app_type] => utility [patent_app_number] => 09/738832 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 9238 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/883/06883087.pdf [firstpage_image] =>[orig_patent_app_number] => 09738832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7080176 [patent_doc_number] => 20010042219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'Technique for pipelining synchronization to maintain throughput across two asynchronous clock domain boundaries' [patent_app_type] => new [patent_app_number] => 09/733590 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4710 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20010042219.pdf [firstpage_image] =>[orig_patent_app_number] => 09733590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6973974 [patent_doc_number] => 20010003834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-14 [patent_title] => 'Interprocessor communication method and multiprocessor' [patent_app_type] => new-utility [patent_app_number] => 09/730533 [patent_app_country] => US [patent_app_date] => 2000-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 20725 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20010003834.pdf [firstpage_image] =>[orig_patent_app_number] => 09730533 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1186386 [patent_doc_number] => 06742109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'Method and apparatus for representing variable-size computer instructions' [patent_app_type] => B2 [patent_app_number] => 09/728737 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2425 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/742/06742109.pdf [firstpage_image] =>[orig_patent_app_number] => 09728737 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1166227 [patent_doc_number] => 06772320 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Method and computer program for data conversion in a heterogeneous communications network' [patent_app_type] => B1 [patent_app_number] => 09/714647 [patent_app_country] => US [patent_app_date] => 2000-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3399 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772320.pdf [firstpage_image] =>[orig_patent_app_number] => 09714647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 950093 [patent_doc_number] => 06963965 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-08 [patent_title] => 'Instruction-programmable processor with instruction loop cache' [patent_app_type] => utility [patent_app_number] => 09/713731 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 12008 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/963/06963965.pdf [firstpage_image] =>[orig_patent_app_number] => 09713731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1139109 [patent_doc_number] => 06789182 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'System and method for logging computer event data and physical components of a complex distributed system' [patent_app_type] => B1 [patent_app_number] => 09/711822 [patent_app_country] => US [patent_app_date] => 2000-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7286 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/789/06789182.pdf [firstpage_image] =>[orig_patent_app_number] => 09711822 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1258457 [patent_doc_number] => 06671797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Microprocessor with expand instruction for forming a mask from one bit' [patent_app_type] => B1 [patent_app_number] => 09/702463 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 11297 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671797.pdf [firstpage_image] =>[orig_patent_app_number] => 09702463 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1185898 [patent_doc_number] => 06745319 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Microprocessor with instructions for shuffling and dealing data' [patent_app_type] => B1 [patent_app_number] => 09/702452 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 8996 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745319.pdf [firstpage_image] =>[orig_patent_app_number] => 09702452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 789425 [patent_doc_number] => 06988189 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-17 [patent_title] => 'Ternary content addressable memory based multi-dimensional multi-way branch selector and method of operating same' [patent_app_type] => utility [patent_app_number] => 09/703337 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4417 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/988/06988189.pdf [firstpage_image] =>[orig_patent_app_number] => 09703337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1124947 [patent_doc_number] => 06799266 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-28 [patent_title] => 'Methods and apparatus for reducing the size of code with an exposed pipeline by encoding NOP operations as instruction operands' [patent_app_type] => B1 [patent_app_number] => 09/702484 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6713 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/799/06799266.pdf [firstpage_image] =>[orig_patent_app_number] => 09702484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1184818 [patent_doc_number] => 06748521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Microprocessor with instruction for saturating and packing data' [patent_app_type] => B1 [patent_app_number] => 09/702476 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 10808 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/748/06748521.pdf [firstpage_image] =>[orig_patent_app_number] => 09702476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1179191 [patent_doc_number] => 06757819 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-29 [patent_title] => 'Microprocessor with instructions for shifting data responsive to a signed count value' [patent_app_type] => B1 [patent_app_number] => 09/703141 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 9593 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757819.pdf [firstpage_image] =>[orig_patent_app_number] => 09703141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1170119 [patent_doc_number] => 06766438 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'RISC processor with a debug interface unit' [patent_app_type] => B1 [patent_app_number] => 09/674352 [patent_app_country] => US [patent_app_date] => 2000-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2307 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766438.pdf [firstpage_image] =>[orig_patent_app_number] => 09674352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1432399 [patent_doc_number] => 06505291 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Processor having a datapath and control logic constituted with basis execution blocks' [patent_app_type] => B1 [patent_app_number] => 09/697911 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 9099 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505291.pdf [firstpage_image] =>[orig_patent_app_number] => 09697911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1169842 [patent_doc_number] => 06763449 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-13 [patent_title] => 'Operation-processing apparatus' [patent_app_type] => B1 [patent_app_number] => 09/693920 [patent_app_country] => US [patent_app_date] => 2000-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 17607 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/763/06763449.pdf [firstpage_image] =>[orig_patent_app_number] => 09693920 [rel_patent_id] =>[rel_patent_doc_number] =>)