Search

Daniel H. Pan

Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2302, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1466696 [patent_doc_number] => 06351804 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Control bit vector storage for a microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/685987 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 12027 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351804.pdf [firstpage_image] =>[orig_patent_app_number] => 09685987 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/685987
Control bit vector storage for a microprocessor Oct 9, 2000 Issued
Array ( [id] => 548924 [patent_doc_number] => 07185184 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-27 [patent_title] => 'Processor system, especially a processor system for communications devices' [patent_app_type] => utility [patent_app_number] => 10/089907 [patent_app_country] => US [patent_app_date] => 2000-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2878 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/185/07185184.pdf [firstpage_image] =>[orig_patent_app_number] => 10089907 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/089907
Processor system, especially a processor system for communications devices Oct 4, 2000 Issued
Array ( [id] => 962210 [patent_doc_number] => 06952763 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-04 [patent_title] => 'Write before read interlock for recovery unit operands' [patent_app_type] => utility [patent_app_number] => 09/677363 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2057 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/952/06952763.pdf [firstpage_image] =>[orig_patent_app_number] => 09677363 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/677363
Write before read interlock for recovery unit operands Oct 1, 2000 Issued
Array ( [id] => 1085041 [patent_doc_number] => 06834337 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-21 [patent_title] => 'System and method for enabling multiple signed independent data elements per register' [patent_app_type] => B1 [patent_app_number] => 09/675779 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5524 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/834/06834337.pdf [firstpage_image] =>[orig_patent_app_number] => 09675779 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/675779
System and method for enabling multiple signed independent data elements per register Sep 28, 2000 Issued
Array ( [id] => 4399556 [patent_doc_number] => 06304901 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Multiple VLAN architecture system' [patent_app_type] => 1 [patent_app_number] => 9/667296 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5289 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304901.pdf [firstpage_image] =>[orig_patent_app_number] => 667296 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/667296
Multiple VLAN architecture system Sep 21, 2000 Issued
Array ( [id] => 524697 [patent_doc_number] => 07197625 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-27 [patent_title] => 'Alignment and ordering of vector elements for single instruction multiple data processing' [patent_app_type] => utility [patent_app_number] => 09/662832 [patent_app_country] => US [patent_app_date] => 2000-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 8950 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/197/07197625.pdf [firstpage_image] =>[orig_patent_app_number] => 09662832 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/662832
Alignment and ordering of vector elements for single instruction multiple data processing Sep 14, 2000 Issued
Array ( [id] => 1161654 [patent_doc_number] => 06775762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Processor and processor system' [patent_app_type] => B1 [patent_app_number] => 09/657349 [patent_app_country] => US [patent_app_date] => 2000-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 29 [patent_no_of_words] => 9223 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775762.pdf [firstpage_image] =>[orig_patent_app_number] => 09657349 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/657349
Processor and processor system Sep 6, 2000 Issued
Array ( [id] => 4424371 [patent_doc_number] => 06266719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'High-throughput interface between a system memory controller and a peripheral device' [patent_app_type] => 1 [patent_app_number] => 9/656192 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 8824 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266719.pdf [firstpage_image] =>[orig_patent_app_number] => 656192 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/656192
High-throughput interface between a system memory controller and a peripheral device Sep 5, 2000 Issued
Array ( [id] => 1210406 [patent_doc_number] => 06718460 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Mechanism for error handling in a computer system' [patent_app_type] => B1 [patent_app_number] => 09/655258 [patent_app_country] => US [patent_app_date] => 2000-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2145 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718460.pdf [firstpage_image] =>[orig_patent_app_number] => 09655258 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/655258
Mechanism for error handling in a computer system Sep 4, 2000 Issued
Array ( [id] => 1183617 [patent_doc_number] => 06751723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Field programmable gate array and microcontroller system-on-a-chip' [patent_app_type] => B1 [patent_app_number] => 09/654237 [patent_app_country] => US [patent_app_date] => 2000-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9638 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751723.pdf [firstpage_image] =>[orig_patent_app_number] => 09654237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654237
Field programmable gate array and microcontroller system-on-a-chip Sep 1, 2000 Issued
Array ( [id] => 4402579 [patent_doc_number] => 06279107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions' [patent_app_type] => 1 [patent_app_number] => 9/654843 [patent_app_country] => US [patent_app_date] => 2000-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 15978 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279107.pdf [firstpage_image] =>[orig_patent_app_number] => 654843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654843
Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions Sep 1, 2000 Issued
Array ( [id] => 1258461 [patent_doc_number] => 06671799 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'System and method for dynamically sizing hardware loops and executing nested loops in a digital signal processor' [patent_app_type] => B1 [patent_app_number] => 09/653494 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4797 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671799.pdf [firstpage_image] =>[orig_patent_app_number] => 09653494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653494
System and method for dynamically sizing hardware loops and executing nested loops in a digital signal processor Aug 30, 2000 Issued
Array ( [id] => 1201030 [patent_doc_number] => 06728866 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Partitioned issue queue and allocation strategy' [patent_app_type] => B1 [patent_app_number] => 09/652049 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4449 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728866.pdf [firstpage_image] =>[orig_patent_app_number] => 09652049 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652049
Partitioned issue queue and allocation strategy Aug 30, 2000 Issued
Array ( [id] => 1181173 [patent_doc_number] => 06754807 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'System and method for managing vertical dependencies in a digital signal processor' [patent_app_type] => B1 [patent_app_number] => 09/652450 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5857 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754807.pdf [firstpage_image] =>[orig_patent_app_number] => 09652450 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652450
System and method for managing vertical dependencies in a digital signal processor Aug 30, 2000 Issued
Array ( [id] => 1474998 [patent_doc_number] => 06408376 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously' [patent_app_type] => B1 [patent_app_number] => 09/652100 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 17193 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408376.pdf [firstpage_image] =>[orig_patent_app_number] => 09652100 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652100
Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously Aug 29, 2000 Issued
Array ( [id] => 1088632 [patent_doc_number] => 06832306 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-14 [patent_title] => 'Method and apparatus for a unified RISC/DSP pipeline controller for both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructions' [patent_app_type] => B1 [patent_app_number] => 09/652593 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 13200 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/832/06832306.pdf [firstpage_image] =>[orig_patent_app_number] => 09652593 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652593
Method and apparatus for a unified RISC/DSP pipeline controller for both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructions Aug 29, 2000 Issued
Array ( [id] => 1210405 [patent_doc_number] => 06718459 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Device and method for arithmetic processing' [patent_app_type] => B1 [patent_app_number] => 09/650040 [patent_app_country] => US [patent_app_date] => 2000-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8063 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718459.pdf [firstpage_image] =>[orig_patent_app_number] => 09650040 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/650040
Device and method for arithmetic processing Aug 28, 2000 Issued
Array ( [id] => 1112186 [patent_doc_number] => 06810474 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Information processor' [patent_app_type] => B1 [patent_app_number] => 09/623182 [patent_app_country] => US [patent_app_date] => 2000-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10724 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/810/06810474.pdf [firstpage_image] =>[orig_patent_app_number] => 09623182 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/623182
Information processor Aug 28, 2000 Issued
Array ( [id] => 1490149 [patent_doc_number] => 06366997 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Methods and apparatus for manarray PE-PE switch control' [patent_app_type] => B1 [patent_app_number] => 09/649647 [patent_app_country] => US [patent_app_date] => 2000-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 46 [patent_no_of_words] => 9261 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366997.pdf [firstpage_image] =>[orig_patent_app_number] => 09649647 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/649647
Methods and apparatus for manarray PE-PE switch control Aug 28, 2000 Issued
Array ( [id] => 1181142 [patent_doc_number] => 06754802 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Single instruction multiple data massively parallel processor systems on a chip and system using same' [patent_app_type] => B1 [patent_app_number] => 09/645580 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4970 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754802.pdf [firstpage_image] =>[orig_patent_app_number] => 09645580 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/645580
Single instruction multiple data massively parallel processor systems on a chip and system using same Aug 24, 2000 Issued
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