Search

Daniel H. Pan

Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2302, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7633063 [patent_doc_number] => 06658557 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Synthesizing the instruction stream executed by a microprocessor from its branch trace data' [patent_app_type] => B1 [patent_app_number] => 09/578953 [patent_app_country] => US [patent_app_date] => 2000-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3705 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658557.pdf [firstpage_image] =>[orig_patent_app_number] => 09578953 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/578953
Synthesizing the instruction stream executed by a microprocessor from its branch trace data May 24, 2000 Issued
Array ( [id] => 1201020 [patent_doc_number] => 06728862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Processor array and parallel data processing methods' [patent_app_type] => B1 [patent_app_number] => 09/576871 [patent_app_country] => US [patent_app_date] => 2000-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 12423 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728862.pdf [firstpage_image] =>[orig_patent_app_number] => 09576871 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/576871
Processor array and parallel data processing methods May 21, 2000 Issued
Array ( [id] => 1337250 [patent_doc_number] => 06604189 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Master/slave processor memory inter accessability in an integrated embedded system' [patent_app_type] => B1 [patent_app_number] => 09/576575 [patent_app_country] => US [patent_app_date] => 2000-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604189.pdf [firstpage_image] =>[orig_patent_app_number] => 09576575 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/576575
Master/slave processor memory inter accessability in an integrated embedded system May 21, 2000 Issued
Array ( [id] => 1179189 [patent_doc_number] => 06757817 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-29 [patent_title] => 'Apparatus having a cache and a loop buffer' [patent_app_type] => B1 [patent_app_number] => 09/574010 [patent_app_country] => US [patent_app_date] => 2000-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3205 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757817.pdf [firstpage_image] =>[orig_patent_app_number] => 09574010 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/574010
Apparatus having a cache and a loop buffer May 18, 2000 Issued
Array ( [id] => 1218208 [patent_doc_number] => 06711665 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Associative processor' [patent_app_type] => B1 [patent_app_number] => 09/572581 [patent_app_country] => US [patent_app_date] => 2000-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11890 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711665.pdf [firstpage_image] =>[orig_patent_app_number] => 09572581 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/572581
Associative processor May 16, 2000 Issued
Array ( [id] => 1308985 [patent_doc_number] => 06629235 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Condition code register architecture for supporting multiple execution units' [patent_app_type] => B1 [patent_app_number] => 09/564943 [patent_app_country] => US [patent_app_date] => 2000-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3822 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629235.pdf [firstpage_image] =>[orig_patent_app_number] => 09564943 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/564943
Condition code register architecture for supporting multiple execution units May 4, 2000 Issued
Array ( [id] => 4333385 [patent_doc_number] => 06317825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Microprocessor comprising bit concatenation means' [patent_app_type] => 1 [patent_app_number] => 9/564093 [patent_app_country] => US [patent_app_date] => 2000-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4942 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317825.pdf [firstpage_image] =>[orig_patent_app_number] => 564093 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/564093
Microprocessor comprising bit concatenation means May 2, 2000 Issued
Array ( [id] => 7626818 [patent_doc_number] => 06807626 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Execution of a computer program' [patent_app_type] => B1 [patent_app_number] => 09/563702 [patent_app_country] => US [patent_app_date] => 2000-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3706 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807626.pdf [firstpage_image] =>[orig_patent_app_number] => 09563702 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/563702
Execution of a computer program May 1, 2000 Issued
Array ( [id] => 1540116 [patent_doc_number] => 06338131 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Network system with TCP/IP ACK reduction' [patent_app_type] => B1 [patent_app_number] => 09/562469 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 8434 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338131.pdf [firstpage_image] =>[orig_patent_app_number] => 09562469 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/562469
Network system with TCP/IP ACK reduction Apr 30, 2000 Issued
Array ( [id] => 1185900 [patent_doc_number] => 06745320 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Data processing apparatus' [patent_app_type] => B1 [patent_app_number] => 09/559571 [patent_app_country] => US [patent_app_date] => 2000-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 102 [patent_no_of_words] => 80217 [patent_no_of_claims] => 89 [patent_no_of_ind_claims] => 33 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745320.pdf [firstpage_image] =>[orig_patent_app_number] => 09559571 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/559571
Data processing apparatus Apr 27, 2000 Issued
Array ( [id] => 1250267 [patent_doc_number] => 06675291 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Hardware device for parallel processing of any instruction within a set of instructions' [patent_app_type] => B1 [patent_app_number] => 09/558792 [patent_app_country] => US [patent_app_date] => 2000-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5353 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675291.pdf [firstpage_image] =>[orig_patent_app_number] => 09558792 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/558792
Hardware device for parallel processing of any instruction within a set of instructions Apr 25, 2000 Issued
Array ( [id] => 1186686 [patent_doc_number] => 06738893 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-18 [patent_title] => 'Method and apparatus for scheduling to reduce space and increase speed of microprocessor operations' [patent_app_type] => B1 [patent_app_number] => 09/557650 [patent_app_country] => US [patent_app_date] => 2000-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4890 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738893.pdf [firstpage_image] =>[orig_patent_app_number] => 09557650 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/557650
Method and apparatus for scheduling to reduce space and increase speed of microprocessor operations Apr 24, 2000 Issued
Array ( [id] => 1553844 [patent_doc_number] => 06347378 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Techniques and circuits for high yield improvements in programmable devices using redundant logic' [patent_app_type] => B1 [patent_app_number] => 09/556772 [patent_app_country] => US [patent_app_date] => 2000-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4539 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347378.pdf [firstpage_image] =>[orig_patent_app_number] => 09556772 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/556772
Techniques and circuits for high yield improvements in programmable devices using redundant logic Apr 23, 2000 Issued
Array ( [id] => 1294983 [patent_doc_number] => 06640299 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Method and apparatus for arbitrating access to a computational engine for use in a video graphics controller' [patent_app_type] => B1 [patent_app_number] => 09/556475 [patent_app_country] => US [patent_app_date] => 2000-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 19726 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/640/06640299.pdf [firstpage_image] =>[orig_patent_app_number] => 09556475 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/556475
Method and apparatus for arbitrating access to a computational engine for use in a video graphics controller Apr 20, 2000 Issued
Array ( [id] => 1058994 [patent_doc_number] => 06857061 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-15 [patent_title] => 'Method and apparatus for obtaining a scalar value directly from a vector register' [patent_app_type] => utility [patent_app_number] => 09/545182 [patent_app_country] => US [patent_app_date] => 2000-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8956 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/857/06857061.pdf [firstpage_image] =>[orig_patent_app_number] => 09545182 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/545182
Method and apparatus for obtaining a scalar value directly from a vector register Apr 6, 2000 Issued
Array ( [id] => 7638599 [patent_doc_number] => 06397322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Integrated intrinsically safe input-output module' [patent_app_type] => B1 [patent_app_number] => 09/540999 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2466 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397322.pdf [firstpage_image] =>[orig_patent_app_number] => 09540999 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/540999
Integrated intrinsically safe input-output module Mar 30, 2000 Issued
Array ( [id] => 7631546 [patent_doc_number] => 06665791 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Method and apparatus for releasing functional units in a multithreaded VLIW processor' [patent_app_type] => B1 [patent_app_number] => 09/538669 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3149 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665791.pdf [firstpage_image] =>[orig_patent_app_number] => 09538669 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/538669
Method and apparatus for releasing functional units in a multithreaded VLIW processor Mar 29, 2000 Issued
Array ( [id] => 1431473 [patent_doc_number] => 06519696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Paired register exchange using renaming register map' [patent_app_type] => B1 [patent_app_number] => 09/538314 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9625 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519696.pdf [firstpage_image] =>[orig_patent_app_number] => 09538314 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/538314
Paired register exchange using renaming register map Mar 29, 2000 Issued
Array ( [id] => 7633060 [patent_doc_number] => 06658560 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Program translator and processor' [patent_app_type] => B1 [patent_app_number] => 09/536308 [patent_app_country] => US [patent_app_date] => 2000-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 35 [patent_no_of_words] => 9582 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658560.pdf [firstpage_image] =>[orig_patent_app_number] => 09536308 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/536308
Program translator and processor Mar 26, 2000 Issued
Array ( [id] => 1325368 [patent_doc_number] => 06615342 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Method and apparatus for object-oriented interrupt system' [patent_app_type] => B1 [patent_app_number] => 09/536237 [patent_app_country] => US [patent_app_date] => 2000-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7376 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/615/06615342.pdf [firstpage_image] =>[orig_patent_app_number] => 09536237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/536237
Method and apparatus for object-oriented interrupt system Mar 26, 2000 Issued
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