Search

Daniel H. Pan

Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2302, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1279628 [patent_doc_number] => 06654874 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Microcomputer systems having compressed instruction processing capability and methods of operating same' [patent_app_type] => B1 [patent_app_number] => 09/536435 [patent_app_country] => US [patent_app_date] => 2000-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5804 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654874.pdf [firstpage_image] =>[orig_patent_app_number] => 09536435 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/536435
Microcomputer systems having compressed instruction processing capability and methods of operating same Mar 26, 2000 Issued
Array ( [id] => 1326904 [patent_doc_number] => 06609191 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'Method and apparatus for speculative microinstruction pairing' [patent_app_type] => B1 [patent_app_number] => 09/520855 [patent_app_country] => US [patent_app_date] => 2000-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 5 [patent_no_of_words] => 7801 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/609/06609191.pdf [firstpage_image] =>[orig_patent_app_number] => 09520855 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/520855
Method and apparatus for speculative microinstruction pairing Mar 6, 2000 Issued
Array ( [id] => 7631547 [patent_doc_number] => 06665790 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Vector register file with arbitrary vector addressing' [patent_app_type] => B1 [patent_app_number] => 09/514497 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5907 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665790.pdf [firstpage_image] =>[orig_patent_app_number] => 09514497 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/514497
Vector register file with arbitrary vector addressing Feb 28, 2000 Issued
Array ( [id] => 1170106 [patent_doc_number] => 06766437 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Composite uniprocessor' [patent_app_type] => B1 [patent_app_number] => 09/514630 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6350 [patent_no_of_claims] => 74 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766437.pdf [firstpage_image] =>[orig_patent_app_number] => 09514630 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/514630
Composite uniprocessor Feb 27, 2000 Issued
Array ( [id] => 1291961 [patent_doc_number] => 06643763 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Register pipe for multi-processing engine environment' [patent_app_type] => B1 [patent_app_number] => 09/514435 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 10080 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643763.pdf [firstpage_image] =>[orig_patent_app_number] => 09514435 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/514435
Register pipe for multi-processing engine environment Feb 27, 2000 Issued
Array ( [id] => 1329215 [patent_doc_number] => 06606700 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-12 [patent_title] => 'DSP with dual-mac processor and dual-mac coprocessor' [patent_app_type] => B1 [patent_app_number] => 09/513979 [patent_app_country] => US [patent_app_date] => 2000-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2521 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606700.pdf [firstpage_image] =>[orig_patent_app_number] => 09513979 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/513979
DSP with dual-mac processor and dual-mac coprocessor Feb 25, 2000 Issued
Array ( [id] => 1258452 [patent_doc_number] => 06671796 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Converting an arbitrary fixed point value to a floating point value' [patent_app_type] => B1 [patent_app_number] => 09/513494 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3647 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671796.pdf [firstpage_image] =>[orig_patent_app_number] => 09513494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/513494
Converting an arbitrary fixed point value to a floating point value Feb 24, 2000 Issued
Array ( [id] => 4349137 [patent_doc_number] => 06321268 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method and apparatus for selectively retrieving information from a source computer using a terrestrial or satellite interface' [patent_app_type] => 1 [patent_app_number] => 9/512269 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 11626 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321268.pdf [firstpage_image] =>[orig_patent_app_number] => 512269 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/512269
Method and apparatus for selectively retrieving information from a source computer using a terrestrial or satellite interface Feb 23, 2000 Issued
Array ( [id] => 7610015 [patent_doc_number] => 06842844 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-11 [patent_title] => 'Parameter memory for hardware accelerator' [patent_app_type] => utility [patent_app_number] => 09/512511 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1997 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842844.pdf [firstpage_image] =>[orig_patent_app_number] => 09512511 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/512511
Parameter memory for hardware accelerator Feb 23, 2000 Issued
Array ( [id] => 1319159 [patent_doc_number] => 06618803 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'System and method for finding and validating the most recent advance load for a given checkload' [patent_app_type] => B1 [patent_app_number] => 09/510282 [patent_app_country] => US [patent_app_date] => 2000-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7556 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618803.pdf [firstpage_image] =>[orig_patent_app_number] => 09510282 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510282
System and method for finding and validating the most recent advance load for a given checkload Feb 20, 2000 Issued
09/505163 Method and apparatus for instruction execution in a data processing system Feb 15, 2000 Abandoned
Array ( [id] => 1430425 [patent_doc_number] => 06526498 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Method and apparatus for retiming in a network of multiple context processing elements' [patent_app_type] => B1 [patent_app_number] => 09/504203 [patent_app_country] => US [patent_app_date] => 2000-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8759 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526498.pdf [firstpage_image] =>[orig_patent_app_number] => 09504203 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/504203
Method and apparatus for retiming in a network of multiple context processing elements Feb 14, 2000 Issued
Array ( [id] => 4423191 [patent_doc_number] => 06311236 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Magnetic disc control apparatus with parallel data transfer between disc control unit and encoder circuit' [patent_app_type] => 1 [patent_app_number] => 9/503248 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 9117 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311236.pdf [firstpage_image] =>[orig_patent_app_number] => 503248 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/503248
Magnetic disc control apparatus with parallel data transfer between disc control unit and encoder circuit Feb 13, 2000 Issued
Array ( [id] => 1357279 [patent_doc_number] => 06591360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Local stall/hazard detect in superscalar, pipelined microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/484138 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7112 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591360.pdf [firstpage_image] =>[orig_patent_app_number] => 09484138 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/484138
Local stall/hazard detect in superscalar, pipelined microprocessor Jan 17, 2000 Issued
Array ( [id] => 1075161 [patent_doc_number] => 06839829 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'Routing protocol based redundancy design for shared-access networks' [patent_app_type] => utility [patent_app_number] => 09/484189 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13840 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839829.pdf [firstpage_image] =>[orig_patent_app_number] => 09484189 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/484189
Routing protocol based redundancy design for shared-access networks Jan 17, 2000 Issued
Array ( [id] => 1325345 [patent_doc_number] => 06615339 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'VLIW processor accepting branching to any instruction in an instruction word set to be executed consecutively' [patent_app_type] => B1 [patent_app_number] => 09/484413 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 10306 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/615/06615339.pdf [firstpage_image] =>[orig_patent_app_number] => 09484413 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/484413
VLIW processor accepting branching to any instruction in an instruction word set to be executed consecutively Jan 17, 2000 Issued
Array ( [id] => 1361578 [patent_doc_number] => 06587940 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Local stall/hazard detect in superscalar, pipelined microprocessor to avoid re-read of register file' [patent_app_type] => B1 [patent_app_number] => 09/483774 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8928 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587940.pdf [firstpage_image] =>[orig_patent_app_number] => 09483774 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/483774
Local stall/hazard detect in superscalar, pipelined microprocessor to avoid re-read of register file Jan 17, 2000 Issued
Array ( [id] => 1206921 [patent_doc_number] => 06721872 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'Reconfigurable network interface architecture' [patent_app_type] => B1 [patent_app_number] => 09/484720 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4230 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721872.pdf [firstpage_image] =>[orig_patent_app_number] => 09484720 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/484720
Reconfigurable network interface architecture Jan 17, 2000 Issued
Array ( [id] => 1406964 [patent_doc_number] => 06560694 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Double prefix overrides to provide 16-bit operand size in a 32/64 operating mode' [patent_app_type] => B1 [patent_app_number] => 09/483755 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 10920 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560694.pdf [firstpage_image] =>[orig_patent_app_number] => 09483755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/483755
Double prefix overrides to provide 16-bit operand size in a 32/64 operating mode Jan 13, 2000 Issued
Array ( [id] => 1214441 [patent_doc_number] => 06715063 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Call gate expansion for 64 bit addressing' [patent_app_type] => B1 [patent_app_number] => 09/483078 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 11028 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715063.pdf [firstpage_image] =>[orig_patent_app_number] => 09483078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/483078
Call gate expansion for 64 bit addressing Jan 13, 2000 Issued
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