Search

Daniel H. Pan

Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2302, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1430445 [patent_doc_number] => 06526500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Data driven type information processing system consisting of interconnected data driven type information processing devices' [patent_app_type] => B1 [patent_app_number] => 09/482881 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 39 [patent_no_of_words] => 9986 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526500.pdf [firstpage_image] =>[orig_patent_app_number] => 09482881 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/482881
Data driven type information processing system consisting of interconnected data driven type information processing devices Jan 13, 2000 Issued
Array ( [id] => 1386088 [patent_doc_number] => 06571330 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Address size and operand size prefix overrides for default sizes defined by an operating mode of a processor' [patent_app_type] => B1 [patent_app_number] => 09/483560 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 10999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571330.pdf [firstpage_image] =>[orig_patent_app_number] => 09483560 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/483560
Address size and operand size prefix overrides for default sizes defined by an operating mode of a processor Jan 13, 2000 Issued
Array ( [id] => 1361564 [patent_doc_number] => 06587939 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Information processing apparatus provided with an optimized executable instruction extracting unit for extending compressed instructions' [patent_app_type] => B1 [patent_app_number] => 09/482262 [patent_app_country] => US [patent_app_date] => 2000-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 6695 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587939.pdf [firstpage_image] =>[orig_patent_app_number] => 09482262 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/482262
Information processing apparatus provided with an optimized executable instruction extracting unit for extending compressed instructions Jan 12, 2000 Issued
Array ( [id] => 1377323 [patent_doc_number] => 06578135 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Method and apparatus for performing addressing operations in a superscalar superpipelined processor' [patent_app_type] => B1 [patent_app_number] => 09/481481 [patent_app_country] => US [patent_app_date] => 2000-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3996 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578135.pdf [firstpage_image] =>[orig_patent_app_number] => 09481481 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/481481
Method and apparatus for performing addressing operations in a superscalar superpipelined processor Jan 10, 2000 Issued
Array ( [id] => 1411976 [patent_doc_number] => 06553487 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Device and method for performing high-speed low overhead context switch' [patent_app_type] => B1 [patent_app_number] => 09/479200 [patent_app_country] => US [patent_app_date] => 2000-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3997 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553487.pdf [firstpage_image] =>[orig_patent_app_number] => 09479200 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/479200
Device and method for performing high-speed low overhead context switch Jan 6, 2000 Issued
Array ( [id] => 1298169 [patent_doc_number] => 06631462 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Memory shared between processing threads' [patent_app_type] => B1 [patent_app_number] => 09/479377 [patent_app_country] => US [patent_app_date] => 2000-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4586 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631462.pdf [firstpage_image] =>[orig_patent_app_number] => 09479377 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/479377
Memory shared between processing threads Jan 4, 2000 Issued
Array ( [id] => 1353480 [patent_doc_number] => 06594755 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'System and method for interleaved execution of multiple independent threads' [patent_app_type] => B1 [patent_app_number] => 09/477512 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3439 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594755.pdf [firstpage_image] =>[orig_patent_app_number] => 09477512 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477512
System and method for interleaved execution of multiple independent threads Jan 3, 2000 Issued
Array ( [id] => 1428992 [patent_doc_number] => 06513101 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Expiring host selected scratch logical volumes in an automated data storage library' [patent_app_type] => B1 [patent_app_number] => 09/477557 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5269 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/513/06513101.pdf [firstpage_image] =>[orig_patent_app_number] => 09477557 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477557
Expiring host selected scratch logical volumes in an automated data storage library Jan 3, 2000 Issued
Array ( [id] => 1357292 [patent_doc_number] => 06591361 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Method and apparatus for converting data into different ordinal types' [patent_app_type] => B1 [patent_app_number] => 09/473760 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1737 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591361.pdf [firstpage_image] =>[orig_patent_app_number] => 09473760 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473760
Method and apparatus for converting data into different ordinal types Dec 27, 1999 Issued
Array ( [id] => 1431920 [patent_doc_number] => 06516407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Information processor' [patent_app_type] => B1 [patent_app_number] => 09/473046 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 35 [patent_no_of_words] => 7994 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516407.pdf [firstpage_image] =>[orig_patent_app_number] => 09473046 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473046
Information processor Dec 27, 1999 Issued
Array ( [id] => 1423631 [patent_doc_number] => 06539468 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Data copying system, data copying method, data reading apparatus, data writing apparatus and data recording medium' [patent_app_type] => B1 [patent_app_number] => 09/472479 [patent_app_country] => US [patent_app_date] => 1999-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6107 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539468.pdf [firstpage_image] =>[orig_patent_app_number] => 09472479 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472479
Data copying system, data copying method, data reading apparatus, data writing apparatus and data recording medium Dec 26, 1999 Issued
Array ( [id] => 1409665 [patent_doc_number] => 06557095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Scheduling operations using a dependency matrix' [patent_app_type] => B1 [patent_app_number] => 09/472165 [patent_app_country] => US [patent_app_date] => 1999-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 7560 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557095.pdf [firstpage_image] =>[orig_patent_app_number] => 09472165 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472165
Scheduling operations using a dependency matrix Dec 26, 1999 Issued
Array ( [id] => 1429913 [patent_doc_number] => 06530076 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Data processing system processor dynamic selection of internal signal tracing' [patent_app_type] => B1 [patent_app_number] => 09/472114 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5917 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/530/06530076.pdf [firstpage_image] =>[orig_patent_app_number] => 09472114 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472114
Data processing system processor dynamic selection of internal signal tracing Dec 22, 1999 Issued
Array ( [id] => 1311472 [patent_doc_number] => 06625725 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Speculative reuse of code regions' [patent_app_type] => B1 [patent_app_number] => 09/470113 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625725.pdf [firstpage_image] =>[orig_patent_app_number] => 09470113 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470113
Speculative reuse of code regions Dec 21, 1999 Issued
Array ( [id] => 1421396 [patent_doc_number] => 06542987 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Method and circuits for early detection of a full queue' [patent_app_type] => B1 [patent_app_number] => 09/465689 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 6964 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542987.pdf [firstpage_image] =>[orig_patent_app_number] => 09465689 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/465689
Method and circuits for early detection of a full queue Dec 16, 1999 Issued
Array ( [id] => 713255 [patent_doc_number] => 07062633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-13 [patent_title] => 'Conditional vector arithmetic method and conditional vector arithmetic unit' [patent_app_type] => utility [patent_app_number] => 09/868048 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8521 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/062/07062633.pdf [firstpage_image] =>[orig_patent_app_number] => 09868048 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/868048
Conditional vector arithmetic method and conditional vector arithmetic unit Dec 14, 1999 Issued
Array ( [id] => 1411926 [patent_doc_number] => 06553484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Instruction-issuing circuit that sets reference dependency information in a preceding instruction when a succeeding instruction is stored in an instruction out-of-order buffer' [patent_app_type] => B1 [patent_app_number] => 09/450769 [patent_app_country] => US [patent_app_date] => 1999-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3398 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553484.pdf [firstpage_image] =>[orig_patent_app_number] => 09450769 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/450769
Instruction-issuing circuit that sets reference dependency information in a preceding instruction when a succeeding instruction is stored in an instruction out-of-order buffer Nov 29, 1999 Issued
Array ( [id] => 1377309 [patent_doc_number] => 06578134 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Multi-branch resolution' [patent_app_type] => B1 [patent_app_number] => 09/451300 [patent_app_country] => US [patent_app_date] => 1999-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5290 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578134.pdf [firstpage_image] =>[orig_patent_app_number] => 09451300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/451300
Multi-branch resolution Nov 28, 1999 Issued
Array ( [id] => 1284635 [patent_doc_number] => 06651159 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Floating point register stack management for CISC' [patent_app_type] => B1 [patent_app_number] => 09/449956 [patent_app_country] => US [patent_app_date] => 1999-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3236 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/651/06651159.pdf [firstpage_image] =>[orig_patent_app_number] => 09449956 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/449956
Floating point register stack management for CISC Nov 28, 1999 Issued
Array ( [id] => 1411906 [patent_doc_number] => 06553483 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Enhanced virtual renaming scheme and deadlock prevention therefor' [patent_app_type] => B1 [patent_app_number] => 09/449520 [patent_app_country] => US [patent_app_date] => 1999-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4857 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553483.pdf [firstpage_image] =>[orig_patent_app_number] => 09449520 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/449520
Enhanced virtual renaming scheme and deadlock prevention therefor Nov 28, 1999 Issued
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