Search

Daniel H. Pan

Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2302, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1416015 [patent_doc_number] => 06550005 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Mechanism for recovery from termination of a program instruction due to an exception in a pipeland processing system' [patent_app_type] => B1 [patent_app_number] => 09/449867 [patent_app_country] => US [patent_app_date] => 1999-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4056 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/550/06550005.pdf [firstpage_image] =>[orig_patent_app_number] => 09449867 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/449867
Mechanism for recovery from termination of a program instruction due to an exception in a pipeland processing system Nov 28, 1999 Issued
Array ( [id] => 1329224 [patent_doc_number] => 06606701 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-12 [patent_title] => 'Micro-processor' [patent_app_type] => B1 [patent_app_number] => 09/448299 [patent_app_country] => US [patent_app_date] => 1999-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12719 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606701.pdf [firstpage_image] =>[orig_patent_app_number] => 09448299 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/448299
Micro-processor Nov 23, 1999 Issued
Array ( [id] => 1431291 [patent_doc_number] => 06523108 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Method of and apparatus for extracting a string of bits from a binary bit string and depositing a string of bits onto a binary bit string' [patent_app_type] => B1 [patent_app_number] => 09/448568 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6067 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523108.pdf [firstpage_image] =>[orig_patent_app_number] => 09448568 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/448568
Method of and apparatus for extracting a string of bits from a binary bit string and depositing a string of bits onto a binary bit string Nov 22, 1999 Issued
Array ( [id] => 1425336 [patent_doc_number] => 06535971 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Data processing system having plurality of processors and executing series of processings in prescribed order' [patent_app_type] => B1 [patent_app_number] => 09/447263 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 48 [patent_no_of_words] => 18187 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535971.pdf [firstpage_image] =>[orig_patent_app_number] => 09447263 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447263
Data processing system having plurality of processors and executing series of processings in prescribed order Nov 22, 1999 Issued
Array ( [id] => 4423988 [patent_doc_number] => 06240531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'System and method for computer operating system protection' [patent_app_type] => 1 [patent_app_number] => 9/447397 [patent_app_country] => US [patent_app_date] => 1999-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9434 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240531.pdf [firstpage_image] =>[orig_patent_app_number] => 447397 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447397
System and method for computer operating system protection Nov 21, 1999 Issued
Array ( [id] => 1425348 [patent_doc_number] => 06535972 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Shared dependency checking for status flags' [patent_app_type] => B1 [patent_app_number] => 09/441631 [patent_app_country] => US [patent_app_date] => 1999-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535972.pdf [firstpage_image] =>[orig_patent_app_number] => 09441631 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/441631
Shared dependency checking for status flags Nov 15, 1999 Issued
Array ( [id] => 1521774 [patent_doc_number] => 06502188 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Dynamic classification of conditional branches in global history branch prediction' [patent_app_type] => B1 [patent_app_number] => 09/441630 [patent_app_country] => US [patent_app_date] => 1999-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 12612 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502188.pdf [firstpage_image] =>[orig_patent_app_number] => 09441630 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/441630
Dynamic classification of conditional branches in global history branch prediction Nov 15, 1999 Issued
Array ( [id] => 1602291 [patent_doc_number] => 06493819 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Merging narrow register for resolution of data dependencies when updating a portion of a register in a microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/442209 [patent_app_country] => US [patent_app_date] => 1999-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9925 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493819.pdf [firstpage_image] =>[orig_patent_app_number] => 09442209 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/442209
Merging narrow register for resolution of data dependencies when updating a portion of a register in a microprocessor Nov 15, 1999 Issued
Array ( [id] => 1423650 [patent_doc_number] => 06539470 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Instruction decode unit producing instruction operand information in the order in which the operands are identified, and systems including same' [patent_app_type] => B1 [patent_app_number] => 09/441632 [patent_app_country] => US [patent_app_date] => 1999-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8980 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539470.pdf [firstpage_image] =>[orig_patent_app_number] => 09441632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/441632
Instruction decode unit producing instruction operand information in the order in which the operands are identified, and systems including same Nov 15, 1999 Issued
Array ( [id] => 4424798 [patent_doc_number] => 06230254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'System and method for handling load and/or store operators in a superscalar microprocessor' [patent_app_type] => 1 [patent_app_number] => 9/438360 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10666 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230254.pdf [firstpage_image] =>[orig_patent_app_number] => 438360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/438360
System and method for handling load and/or store operators in a superscalar microprocessor Nov 11, 1999 Issued
Array ( [id] => 4325844 [patent_doc_number] => 06253316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Three state branch history using one bit in a branch prediction mechanism' [patent_app_type] => 1 [patent_app_number] => 9/438963 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 16632 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253316.pdf [firstpage_image] =>[orig_patent_app_number] => 438963 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/438963
Three state branch history using one bit in a branch prediction mechanism Nov 11, 1999 Issued
Array ( [id] => 1604507 [patent_doc_number] => 06434693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'System and method for handling load and/or store operations in a superscalar microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/438359 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10841 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434693.pdf [firstpage_image] =>[orig_patent_app_number] => 09438359 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/438359
System and method for handling load and/or store operations in a superscalar microprocessor Nov 11, 1999 Issued
Array ( [id] => 4422641 [patent_doc_number] => 06272619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'High-performance, superscalar-based computer system with out-of-order instruction execution' [patent_app_type] => 1 [patent_app_number] => 9/437601 [patent_app_country] => US [patent_app_date] => 1999-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 31518 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272619.pdf [firstpage_image] =>[orig_patent_app_number] => 437601 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/437601
High-performance, superscalar-based computer system with out-of-order instruction execution Nov 9, 1999 Issued
Array ( [id] => 4381398 [patent_doc_number] => 06256720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'High performance, superscalar-based computer system with out-of-order instruction execution' [patent_app_type] => 1 [patent_app_number] => 9/436986 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 31527 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256720.pdf [firstpage_image] =>[orig_patent_app_number] => 436986 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/436986
High performance, superscalar-based computer system with out-of-order instruction execution Nov 8, 1999 Issued
Array ( [id] => 1456819 [patent_doc_number] => 06457120 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Processor and method including a cache having confirmation bits for improving address predictable branch instruction target predictions' [patent_app_type] => B1 [patent_app_number] => 09/431369 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4255 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457120.pdf [firstpage_image] =>[orig_patent_app_number] => 09431369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/431369
Processor and method including a cache having confirmation bits for improving address predictable branch instruction target predictions Oct 31, 1999 Issued
09/431801 A MICROPROCESSOR Oct 31, 1999 Abandoned
Array ( [id] => 7642362 [patent_doc_number] => 06430684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Processor circuits, systems, and methods with efficient granularity shift and/or merge instruction(s)' [patent_app_type] => B1 [patent_app_number] => 09/431562 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 19 [patent_no_of_words] => 7445 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430684.pdf [firstpage_image] =>[orig_patent_app_number] => 09431562 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/431562
Processor circuits, systems, and methods with efficient granularity shift and/or merge instruction(s) Oct 28, 1999 Issued
Array ( [id] => 1431296 [patent_doc_number] => 06523109 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Store queue multimatch detection' [patent_app_type] => B1 [patent_app_number] => 09/433189 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 15042 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523109.pdf [firstpage_image] =>[orig_patent_app_number] => 09433189 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/433189
Store queue multimatch detection Oct 24, 1999 Issued
Array ( [id] => 1567479 [patent_doc_number] => 06438677 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Dynamic handling of object versions to support space and time dimensional program execution' [patent_app_type] => B1 [patent_app_number] => 09/422028 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 5853 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438677.pdf [firstpage_image] =>[orig_patent_app_number] => 09422028 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/422028
Dynamic handling of object versions to support space and time dimensional program execution Oct 19, 1999 Issued
Array ( [id] => 1429375 [patent_doc_number] => 06530011 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Method and apparatus for vector register with scalar values' [patent_app_type] => B1 [patent_app_number] => 09/422045 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 5444 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/530/06530011.pdf [firstpage_image] =>[orig_patent_app_number] => 09422045 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/422045
Method and apparatus for vector register with scalar values Oct 19, 1999 Issued
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