Search

Daniel H. Pan

Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2302, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1540611 [patent_doc_number] => 06490676 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Method and apparatus for protecting against failures due to data unavailability in real-time data processing' [patent_app_type] => B1 [patent_app_number] => 09/364006 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5831 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490676.pdf [firstpage_image] =>[orig_patent_app_number] => 09364006 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364006
Method and apparatus for protecting against failures due to data unavailability in real-time data processing Jul 28, 1999 Issued
Array ( [id] => 1524860 [patent_doc_number] => 06415354 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Pipelined methods and apparatus for weight selection and content addressable memory searches' [patent_app_type] => B1 [patent_app_number] => 09/354684 [patent_app_country] => US [patent_app_date] => 1999-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4815 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415354.pdf [firstpage_image] =>[orig_patent_app_number] => 09354684 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/354684
Pipelined methods and apparatus for weight selection and content addressable memory searches Jul 14, 1999 Issued
Array ( [id] => 4388471 [patent_doc_number] => 06275922 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method and apparatus for remotely managing multiple appliance control configurations' [patent_app_type] => 1 [patent_app_number] => 9/348845 [patent_app_country] => US [patent_app_date] => 1999-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7215 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275922.pdf [firstpage_image] =>[orig_patent_app_number] => 348845 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/348845
Method and apparatus for remotely managing multiple appliance control configurations Jul 6, 1999 Issued
Array ( [id] => 1539261 [patent_doc_number] => 06412062 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Injection control mechanism for external events' [patent_app_type] => B1 [patent_app_number] => 09/343972 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2741 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412062.pdf [firstpage_image] =>[orig_patent_app_number] => 09343972 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343972
Injection control mechanism for external events Jun 29, 1999 Issued
Array ( [id] => 1602061 [patent_doc_number] => 06385719 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/345719 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3805 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385719.pdf [firstpage_image] =>[orig_patent_app_number] => 09345719 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/345719
Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor Jun 29, 1999 Issued
Array ( [id] => 1540610 [patent_doc_number] => 06490675 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Converter and conversion method' [patent_app_type] => B1 [patent_app_number] => 09/342916 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 5105 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490675.pdf [firstpage_image] =>[orig_patent_app_number] => 09342916 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/342916
Converter and conversion method Jun 29, 1999 Issued
Array ( [id] => 1567503 [patent_doc_number] => 06363474 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Process switching register replication in a data processing system' [patent_app_type] => B1 [patent_app_number] => 09/345229 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8574 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363474.pdf [firstpage_image] =>[orig_patent_app_number] => 09345229 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/345229
Process switching register replication in a data processing system Jun 29, 1999 Issued
Array ( [id] => 1444126 [patent_doc_number] => 06496921 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Layered speculative request unit with instruction optimized and storage hierarchy optimized partitions' [patent_app_type] => B1 [patent_app_number] => 09/345643 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6106 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496921.pdf [firstpage_image] =>[orig_patent_app_number] => 09345643 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/345643
Layered speculative request unit with instruction optimized and storage hierarchy optimized partitions Jun 29, 1999 Issued
Array ( [id] => 4424167 [patent_doc_number] => 06301651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Method and apparatus for folding a plurality of instructions' [patent_app_type] => 1 [patent_app_number] => 9/340405 [patent_app_country] => US [patent_app_date] => 1999-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7444 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301651.pdf [firstpage_image] =>[orig_patent_app_number] => 340405 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/340405
Method and apparatus for folding a plurality of instructions Jun 27, 1999 Issued
Array ( [id] => 1466324 [patent_doc_number] => 06393553 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Acknowledgement mechanism for just-in-time delivery of load data' [patent_app_type] => B1 [patent_app_number] => 09/344060 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7726 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393553.pdf [firstpage_image] =>[orig_patent_app_number] => 09344060 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344060
Acknowledgement mechanism for just-in-time delivery of load data Jun 24, 1999 Issued
Array ( [id] => 7642363 [patent_doc_number] => 06430683 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Processor and method for just-in-time delivery of load data via time dependency field' [patent_app_type] => B1 [patent_app_number] => 09/344023 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7720 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430683.pdf [firstpage_image] =>[orig_patent_app_number] => 09344023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344023
Processor and method for just-in-time delivery of load data via time dependency field Jun 24, 1999 Issued
Array ( [id] => 1314608 [patent_doc_number] => 06622239 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Method, system and computer program product for optimization of single byte character processing employed within a multibyte character encoding scheme' [patent_app_type] => B1 [patent_app_number] => 09/339883 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4779 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622239.pdf [firstpage_image] =>[orig_patent_app_number] => 09339883 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/339883
Method, system and computer program product for optimization of single byte character processing employed within a multibyte character encoding scheme Jun 24, 1999 Issued
Array ( [id] => 1539284 [patent_doc_number] => 06412065 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Status register associated with MMX register file for tracking writes' [patent_app_type] => B1 [patent_app_number] => 09/344439 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2763 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412065.pdf [firstpage_image] =>[orig_patent_app_number] => 09344439 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344439
Status register associated with MMX register file for tracking writes Jun 24, 1999 Issued
Array ( [id] => 4199251 [patent_doc_number] => 06038654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'High performance, superscalar-based computer system with out-of-order instruction execution' [patent_app_type] => 1 [patent_app_number] => 9/338563 [patent_app_country] => US [patent_app_date] => 1999-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 31661 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038654.pdf [firstpage_image] =>[orig_patent_app_number] => 338563 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/338563
High performance, superscalar-based computer system with out-of-order instruction execution Jun 22, 1999 Issued
Array ( [id] => 1460060 [patent_doc_number] => 06463521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Opcode numbering for meta-data encoding' [patent_app_type] => B1 [patent_app_number] => 09/338875 [patent_app_country] => US [patent_app_date] => 1999-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 4621 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463521.pdf [firstpage_image] =>[orig_patent_app_number] => 09338875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/338875
Opcode numbering for meta-data encoding Jun 22, 1999 Issued
Array ( [id] => 7645887 [patent_doc_number] => 06477636 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Application-specific integrated circuit for processing defined sequences of assembler instructions' [patent_app_type] => B1 [patent_app_number] => 09/337639 [patent_app_country] => US [patent_app_date] => 1999-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3457 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477636.pdf [firstpage_image] =>[orig_patent_app_number] => 09337639 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/337639
Application-specific integrated circuit for processing defined sequences of assembler instructions Jun 21, 1999 Issued
Array ( [id] => 1192498 [patent_doc_number] => 06735685 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'System and method for handling load and/or store operations in a superscalar microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/336589 [patent_app_country] => US [patent_app_date] => 1999-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10864 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735685.pdf [firstpage_image] =>[orig_patent_app_number] => 09336589 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/336589
System and method for handling load and/or store operations in a superscalar microprocessor Jun 20, 1999 Issued
Array ( [id] => 7642365 [patent_doc_number] => 06430681 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Digital signal processor' [patent_app_type] => B1 [patent_app_number] => 09/336075 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5656 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430681.pdf [firstpage_image] =>[orig_patent_app_number] => 09336075 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/336075
Digital signal processor Jun 17, 1999 Issued
Array ( [id] => 1466680 [patent_doc_number] => 06351798 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Address resolution unit and address resolution method for a multiprocessor system' [patent_app_type] => B1 [patent_app_number] => 09/333051 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2920 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351798.pdf [firstpage_image] =>[orig_patent_app_number] => 09333051 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333051
Address resolution unit and address resolution method for a multiprocessor system Jun 14, 1999 Issued
Array ( [id] => 4412527 [patent_doc_number] => 06298436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method and system for performing atomic memory accesses in a processor system' [patent_app_type] => 1 [patent_app_number] => 9/327644 [patent_app_country] => US [patent_app_date] => 1999-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4802 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298436.pdf [firstpage_image] =>[orig_patent_app_number] => 327644 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/327644
Method and system for performing atomic memory accesses in a processor system Jun 7, 1999 Issued
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