
Daniel H. Pan
Examiner (ID: 18277)
| Most Active Art Unit | 2182 |
| Art Unit(s) | 2302, 2182, 2183, 2783, 2315, 2899 |
| Total Applications | 1471 |
| Issued Applications | 1279 |
| Pending Applications | 50 |
| Abandoned Applications | 145 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16683263
[patent_doc_number] => 10942741
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-09
[patent_title] => Storage organization for transposing a matrix using a streaming engine
[patent_app_type] => utility
[patent_app_number] => 16/282508
[patent_app_country] => US
[patent_app_date] => 2019-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 49
[patent_no_of_words] => 32499
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16282508
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/282508 | Storage organization for transposing a matrix using a streaming engine | Feb 21, 2019 | Issued |
Array
(
[id] => 16698609
[patent_doc_number] => 10949206
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-16
[patent_title] => Transposing a matrix using a streaming engine
[patent_app_type] => utility
[patent_app_number] => 16/282526
[patent_app_country] => US
[patent_app_date] => 2019-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 49
[patent_no_of_words] => 32416
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16282526
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/282526 | Transposing a matrix using a streaming engine | Feb 21, 2019 | Issued |
Array
(
[id] => 16607897
[patent_doc_number] => 10908900
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-02-02
[patent_title] => Efficient mapping of input data to vectors for a predictive model
[patent_app_type] => utility
[patent_app_number] => 16/277817
[patent_app_country] => US
[patent_app_date] => 2019-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5198
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16277817
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/277817 | Efficient mapping of input data to vectors for a predictive model | Feb 14, 2019 | Issued |
Array
(
[id] => 16292083
[patent_doc_number] => 10768933
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-08
[patent_title] => Streaming engine with stream metadata saving for context switching
[patent_app_type] => utility
[patent_app_number] => 16/273413
[patent_app_country] => US
[patent_app_date] => 2019-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 40
[patent_no_of_words] => 22920
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16273413
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/273413 | Streaming engine with stream metadata saving for context switching | Feb 11, 2019 | Issued |
Array
(
[id] => 16208941
[patent_doc_number] => 20200241931
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-30
[patent_title] => SUPPORTING SPECULATIVE MICROPROCESSOR INSTRUCTION EXECUTION
[patent_app_type] => utility
[patent_app_number] => 16/257259
[patent_app_country] => US
[patent_app_date] => 2019-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5207
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16257259
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/257259 | Supporting speculative microprocessor instruction execution | Jan 24, 2019 | Issued |
Array
(
[id] => 16208941
[patent_doc_number] => 20200241931
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-30
[patent_title] => SUPPORTING SPECULATIVE MICROPROCESSOR INSTRUCTION EXECUTION
[patent_app_type] => utility
[patent_app_number] => 16/257259
[patent_app_country] => US
[patent_app_date] => 2019-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5207
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16257259
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/257259 | Supporting speculative microprocessor instruction execution | Jan 24, 2019 | Issued |
Array
(
[id] => 16031803
[patent_doc_number] => 10678319
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-09
[patent_title] => Multi-level loops for computer processor control
[patent_app_type] => utility
[patent_app_number] => 16/252012
[patent_app_country] => US
[patent_app_date] => 2019-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 16816
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16252012
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/252012 | Multi-level loops for computer processor control | Jan 17, 2019 | Issued |
Array
(
[id] => 16129861
[patent_doc_number] => 10698690
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-30
[patent_title] => Synchronisation of execution threads on a multi-threaded processor
[patent_app_type] => utility
[patent_app_number] => 16/251620
[patent_app_country] => US
[patent_app_date] => 2019-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2552
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16251620
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/251620 | Synchronisation of execution threads on a multi-threaded processor | Jan 17, 2019 | Issued |
Array
(
[id] => 16065009
[patent_doc_number] => 10691454
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-23
[patent_title] => Conflict mask generation
[patent_app_type] => utility
[patent_app_number] => 16/249134
[patent_app_country] => US
[patent_app_date] => 2019-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 15053
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249134
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/249134 | Conflict mask generation | Jan 15, 2019 | Issued |
Array
(
[id] => 14347265
[patent_doc_number] => 20190155605
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-23
[patent_title] => Tracking Streaming Engine Vector Predicates to Control Processor Execution
[patent_app_type] => utility
[patent_app_number] => 16/237547
[patent_app_country] => US
[patent_app_date] => 2018-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 29426
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237547
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/237547 | Tracking streaming engine vector predicates to control processor execution | Dec 30, 2018 | Issued |
Array
(
[id] => 16095291
[patent_doc_number] => 20200201632
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-25
[patent_title] => SHIFT-FOLDING FOR EFFICIENT LOAD COALESCING IN A BINARY TRANSLATION BASED PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 16/231305
[patent_app_country] => US
[patent_app_date] => 2018-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19214
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231305
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/231305 | Shift-folding for efficient load coalescing in a binary translation based processor | Dec 20, 2018 | Issued |
Array
(
[id] => 16844691
[patent_doc_number] => 11016776
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-25
[patent_title] => System and method for executing instructions
[patent_app_type] => utility
[patent_app_number] => 16/231280
[patent_app_country] => US
[patent_app_date] => 2018-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6786
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231280
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/231280 | System and method for executing instructions | Dec 20, 2018 | Issued |
Array
(
[id] => 16095317
[patent_doc_number] => 20200201645
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-25
[patent_title] => METHOD AND APPARATUS FOR SUPPORTING SPECULATIVE MEMORY OPTIMIZATIONS
[patent_app_type] => utility
[patent_app_number] => 16/231313
[patent_app_country] => US
[patent_app_date] => 2018-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12140
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231313
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/231313 | Method and apparatus for supporting speculative memory optimizations | Dec 20, 2018 | Issued |
Array
(
[id] => 16095323
[patent_doc_number] => 20200201648
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-25
[patent_title] => Intelligent Scheduling of Coprocessor Execution
[patent_app_type] => utility
[patent_app_number] => 16/226695
[patent_app_country] => US
[patent_app_date] => 2018-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7641
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -33
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226695
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/226695 | Intelligent scheduling of coprocessor execution | Dec 19, 2018 | Issued |
Array
(
[id] => 15820535
[patent_doc_number] => 10635447
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-28
[patent_title] => Scatter reduction instruction
[patent_app_type] => utility
[patent_app_number] => 16/227383
[patent_app_country] => US
[patent_app_date] => 2018-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 17373
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16227383
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/227383 | Scatter reduction instruction | Dec 19, 2018 | Issued |
Array
(
[id] => 14314173
[patent_doc_number] => 20190146790
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-16
[patent_title] => HIGHLY INTEGRATED SCALABLE, FLEXIBLE DSP MEGAMODULE ARCHITECTURE
[patent_app_type] => utility
[patent_app_number] => 16/227238
[patent_app_country] => US
[patent_app_date] => 2018-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16782
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16227238
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/227238 | Highly integrated scalable, flexible DSP megamodule architecture | Dec 19, 2018 | Issued |
Array
(
[id] => 16095161
[patent_doc_number] => 20200201567
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-25
[patent_title] => DEVICE, SYSTEM AND METHOD TO DETECT AN UNINITIALIZED MEMORY READ
[patent_app_type] => utility
[patent_app_number] => 16/228374
[patent_app_country] => US
[patent_app_date] => 2018-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13134
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228374
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/228374 | Device, system and method to detect an uninitialized memory read | Dec 19, 2018 | Issued |
Array
(
[id] => 16416541
[patent_doc_number] => 10824433
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-03
[patent_title] => Array-based inference engine for machine learning
[patent_app_type] => utility
[patent_app_number] => 16/226539
[patent_app_country] => US
[patent_app_date] => 2018-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 12771
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226539
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/226539 | Array-based inference engine for machine learning | Dec 18, 2018 | Issued |
Array
(
[id] => 14188939
[patent_doc_number] => 20190114175
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-18
[patent_title] => SPIN LOOP DELAY INSTRUCTION
[patent_app_type] => utility
[patent_app_number] => 16/212157
[patent_app_country] => US
[patent_app_date] => 2018-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7407
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16212157
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/212157 | Spin loop delay instruction | Dec 5, 2018 | Issued |
Array
(
[id] => 17151737
[patent_doc_number] => 11144815
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-12
[patent_title] => System and architecture of neural network accelerator
[patent_app_type] => utility
[patent_app_number] => 16/769171
[patent_app_country] => US
[patent_app_date] => 2018-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 27153
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16769171
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/769171 | System and architecture of neural network accelerator | Dec 2, 2018 | Issued |