Search

Daniel H. Pan

Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2302, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4294903 [patent_doc_number] => 06324639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Instruction converting apparatus using parallel execution code' [patent_app_type] => 1 [patent_app_number] => 9/280777 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 67 [patent_no_of_words] => 19806 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324639.pdf [firstpage_image] =>[orig_patent_app_number] => 280777 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/280777
Instruction converting apparatus using parallel execution code Mar 28, 1999 Issued
Array ( [id] => 4375603 [patent_doc_number] => 06219699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Multiple VLAN Architecture system' [patent_app_type] => 1 [patent_app_number] => 9/277329 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5311 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219699.pdf [firstpage_image] =>[orig_patent_app_number] => 277329 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/277329
Multiple VLAN Architecture system Mar 25, 1999 Issued
Array ( [id] => 4422631 [patent_doc_number] => 06272618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'System and method for handling interrupts in a multi-processor computer' [patent_app_type] => 1 [patent_app_number] => 9/275826 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2553 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272618.pdf [firstpage_image] =>[orig_patent_app_number] => 275826 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/275826
System and method for handling interrupts in a multi-processor computer Mar 24, 1999 Issued
Array ( [id] => 4304891 [patent_doc_number] => 06269437 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Duplicator interconnection methods and apparatus for reducing port pressure in a clustered processor' [patent_app_type] => 1 [patent_app_number] => 9/274129 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 8608 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269437.pdf [firstpage_image] =>[orig_patent_app_number] => 274129 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/274129
Duplicator interconnection methods and apparatus for reducing port pressure in a clustered processor Mar 21, 1999 Issued
Array ( [id] => 1434054 [patent_doc_number] => 06341344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Apparatus and method for manipulating data for aligning the stack memory' [patent_app_type] => B1 [patent_app_number] => 09/271386 [patent_app_country] => US [patent_app_date] => 1999-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3258 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341344.pdf [firstpage_image] =>[orig_patent_app_number] => 09271386 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/271386
Apparatus and method for manipulating data for aligning the stack memory Mar 17, 1999 Issued
Array ( [id] => 4352140 [patent_doc_number] => 06314514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Method and apparatus for correcting an internal call/return stack in a microprocessor that speculatively executes call and return instructions' [patent_app_type] => 1 [patent_app_number] => 9/271591 [patent_app_country] => US [patent_app_date] => 1999-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5576 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314514.pdf [firstpage_image] =>[orig_patent_app_number] => 271591 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/271591
Method and apparatus for correcting an internal call/return stack in a microprocessor that speculatively executes call and return instructions Mar 17, 1999 Issued
Array ( [id] => 1552974 [patent_doc_number] => 06446190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor' [patent_app_type] => B1 [patent_app_number] => 09/267570 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 8808 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446190.pdf [firstpage_image] =>[orig_patent_app_number] => 09267570 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/267570
Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor Mar 11, 1999 Issued
Array ( [id] => 1540123 [patent_doc_number] => 06338133 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Measured, allocation of speculative branch instructions to processor execution units' [patent_app_type] => B1 [patent_app_number] => 09/267200 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5367 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338133.pdf [firstpage_image] =>[orig_patent_app_number] => 09267200 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/267200
Measured, allocation of speculative branch instructions to processor execution units Mar 11, 1999 Issued
Array ( [id] => 1557349 [patent_doc_number] => 06349380 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/267796 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4001 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349380.pdf [firstpage_image] =>[orig_patent_app_number] => 09267796 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/267796
Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor Mar 11, 1999 Issued
Array ( [id] => 1572459 [patent_doc_number] => 06378064 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Microcomputer' [patent_app_type] => B1 [patent_app_number] => 09/267057 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 13093 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378064.pdf [firstpage_image] =>[orig_patent_app_number] => 09267057 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/267057
Microcomputer Mar 11, 1999 Issued
Array ( [id] => 1326888 [patent_doc_number] => 06609189 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'Cycle segmented prefix circuits' [patent_app_type] => B1 [patent_app_number] => 09/267827 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 65 [patent_no_of_words] => 41251 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/609/06609189.pdf [firstpage_image] =>[orig_patent_app_number] => 09267827 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/267827
Cycle segmented prefix circuits Mar 11, 1999 Issued
Array ( [id] => 4316518 [patent_doc_number] => 06199155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Data processor' [patent_app_type] => 1 [patent_app_number] => 9/267135 [patent_app_country] => US [patent_app_date] => 1999-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 16939 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199155.pdf [firstpage_image] =>[orig_patent_app_number] => 267135 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/267135
Data processor Mar 10, 1999 Issued
Array ( [id] => 1540113 [patent_doc_number] => 06338130 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Adaptive method and apparatus for allocation of DSP resources in a communication system' [patent_app_type] => B1 [patent_app_number] => 09/267888 [patent_app_country] => US [patent_app_date] => 1999-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 10753 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338130.pdf [firstpage_image] =>[orig_patent_app_number] => 09267888 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/267888
Adaptive method and apparatus for allocation of DSP resources in a communication system Mar 10, 1999 Issued
Array ( [id] => 4366372 [patent_doc_number] => 06286094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method and system for optimizing the fetching of dispatch groups in a superscalar processor' [patent_app_type] => 1 [patent_app_number] => 9/263663 [patent_app_country] => US [patent_app_date] => 1999-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2993 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286094.pdf [firstpage_image] =>[orig_patent_app_number] => 263663 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/263663
Method and system for optimizing the fetching of dispatch groups in a superscalar processor Mar 4, 1999 Issued
Array ( [id] => 4424172 [patent_doc_number] => 06266686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Emptying packed data state during execution of packed data instructions' [patent_app_type] => 1 [patent_app_number] => 9/262951 [patent_app_country] => US [patent_app_date] => 1999-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 32555 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266686.pdf [firstpage_image] =>[orig_patent_app_number] => 262951 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/262951
Emptying packed data state during execution of packed data instructions Mar 3, 1999 Issued
Array ( [id] => 4374188 [patent_doc_number] => 06292881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Microprocessor, operation process execution method and recording medium' [patent_app_type] => 1 [patent_app_number] => 9/257198 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 16476 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292881.pdf [firstpage_image] =>[orig_patent_app_number] => 257198 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/257198
Microprocessor, operation process execution method and recording medium Feb 24, 1999 Issued
Array ( [id] => 4426657 [patent_doc_number] => 06178496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'System for converting instructions, and method therefore' [patent_app_type] => 1 [patent_app_number] => 9/251161 [patent_app_country] => US [patent_app_date] => 1999-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6195 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178496.pdf [firstpage_image] =>[orig_patent_app_number] => 251161 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/251161
System for converting instructions, and method therefore Feb 16, 1999 Issued
Array ( [id] => 1553009 [patent_doc_number] => 06446196 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method apparatus and computer program product including one-of and one-of-and-jump instructions for processing data communications' [patent_app_type] => B1 [patent_app_number] => 09/251837 [patent_app_country] => US [patent_app_date] => 1999-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2412 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446196.pdf [firstpage_image] =>[orig_patent_app_number] => 09251837 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/251837
Method apparatus and computer program product including one-of and one-of-and-jump instructions for processing data communications Feb 16, 1999 Issued
Array ( [id] => 4337310 [patent_doc_number] => 06249858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Information processing apparatus having a CPU and an auxiliary arithmetic unit for achieving high-speed operation' [patent_app_type] => 1 [patent_app_number] => 9/250134 [patent_app_country] => US [patent_app_date] => 1999-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 9154 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249858.pdf [firstpage_image] =>[orig_patent_app_number] => 250134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/250134
Information processing apparatus having a CPU and an auxiliary arithmetic unit for achieving high-speed operation Feb 15, 1999 Issued
Array ( [id] => 1490157 [patent_doc_number] => 06367002 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Apparatus and method for fetching instructions for a program-controlled unit' [patent_app_type] => B1 [patent_app_number] => 09/250365 [patent_app_country] => US [patent_app_date] => 1999-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3476 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/367/06367002.pdf [firstpage_image] =>[orig_patent_app_number] => 09250365 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/250365
Apparatus and method for fetching instructions for a program-controlled unit Feb 11, 1999 Issued
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