Daniel H. Pan

Array ( [id] => 1456438 [patent_doc_number] => 06457024 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Wearable hypermedium system' [patent_app_type] => B1 [patent_app_number] => 09/114871 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8945 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457024.pdf [firstpage_image] =>[orig_patent_app_number] => 09114871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3961927 [patent_doc_number] => 05974533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Data processor' [patent_app_type] => 1 [patent_app_number] => 9/113550 [patent_app_country] => US [patent_app_date] => 1998-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 8298 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974533.pdf [firstpage_image] =>[orig_patent_app_number] => 113550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4176817 [patent_doc_number] => 06157994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Microprocessor employing and method of using a control bit vector storage for instruction execution' [patent_app_type] => 1 [patent_app_number] => 9/111572 [patent_app_country] => US [patent_app_date] => 1998-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11734 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157994.pdf [firstpage_image] =>[orig_patent_app_number] => 111572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4260012 [patent_doc_number] => 06167475 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Data transfer method/engine for pipelining shared memory bus accesses' [patent_app_type] => 1 [patent_app_number] => 9/111110 [patent_app_country] => US [patent_app_date] => 1998-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5065 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167475.pdf [firstpage_image] =>[orig_patent_app_number] => 111110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4378975 [patent_doc_number] => 06192410 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Methods and structures for robust, reliable file exchange between secured systems' [patent_app_type] => 1 [patent_app_number] => 9/110218 [patent_app_country] => US [patent_app_date] => 1998-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 20657 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192410.pdf [firstpage_image] =>[orig_patent_app_number] => 110218 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317940 [patent_doc_number] => 06185673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Apparatus and method for array bounds checking with a shadow register file' [patent_app_type] => 1 [patent_app_number] => 9/107243 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2336 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185673.pdf [firstpage_image] =>[orig_patent_app_number] => 107243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4193171 [patent_doc_number] => 06141773 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method and apparatus for undoing changes to computer memory' [patent_app_type] => 1 [patent_app_number] => 9/107891 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 16179 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141773.pdf [firstpage_image] =>[orig_patent_app_number] => 107891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4167448 [patent_doc_number] => 06065112 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Microprocessor with arithmetic processing units and arithmetic execution unit' [patent_app_type] => 1 [patent_app_number] => 9/098448 [patent_app_country] => US [patent_app_date] => 1998-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 10882 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065112.pdf [firstpage_image] =>[orig_patent_app_number] => 098448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4268781 [patent_doc_number] => 06138189 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Network interface having adaptive transmit start point for each packet to avoid transmit underflow' [patent_app_type] => 1 [patent_app_number] => 9/098434 [patent_app_country] => US [patent_app_date] => 1998-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3672 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138189.pdf [firstpage_image] =>[orig_patent_app_number] => 098434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4202163 [patent_doc_number] => 06094692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Network interface having adaptive transmit start point for each packet to avoid transmit underflow' [patent_app_type] => 1 [patent_app_number] => 9/098435 [patent_app_country] => US [patent_app_date] => 1998-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3673 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094692.pdf [firstpage_image] =>[orig_patent_app_number] => 098435 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4427311 [patent_doc_number] => 06226734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method and apparatus for processor migration from different processor states in a multi-processor computer system' [patent_app_type] => 1 [patent_app_number] => 9/090027 [patent_app_country] => US [patent_app_date] => 1998-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 17795 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226734.pdf [firstpage_image] =>[orig_patent_app_number] => 090027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4109835 [patent_doc_number] => 06134624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'High bandwidth cache system' [patent_app_type] => 1 [patent_app_number] => 9/093140 [patent_app_country] => US [patent_app_date] => 1998-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8470 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134624.pdf [firstpage_image] =>[orig_patent_app_number] => 093140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3969027 [patent_doc_number] => 05948090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Method and apparatus for controlling reset of component boards in a computer system' [patent_app_type] => 1 [patent_app_number] => 9/092681 [patent_app_country] => US [patent_app_date] => 1998-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4035 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/948/05948090.pdf [firstpage_image] =>[orig_patent_app_number] => 092681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3916160 [patent_doc_number] => 05951677 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Efficient hardware implementation of euclidean array processing in reed-solomon decoding' [patent_app_type] => 1 [patent_app_number] => 9/086997 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 15957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951677.pdf [firstpage_image] =>[orig_patent_app_number] => 086997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3961344 [patent_doc_number] => 05974495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Using a back-off signal to bridge a first bus to a second bus' [patent_app_type] => 1 [patent_app_number] => 9/087229 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 15800 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974495.pdf [firstpage_image] =>[orig_patent_app_number] => 087229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1533194 [patent_doc_number] => 06480952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Emulation coprocessor' [patent_app_type] => B2 [patent_app_number] => 09/085187 [patent_app_country] => US [patent_app_date] => 1998-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480952.pdf [firstpage_image] =>[orig_patent_app_number] => 09085187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4290419 [patent_doc_number] => 06308255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Symmetrical multiprocessing bus and chipset used for coprocessor support allowing non-native code to run in a system' [patent_app_type] => 1 [patent_app_number] => 9/085188 [patent_app_country] => US [patent_app_date] => 1998-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9091 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308255.pdf [firstpage_image] =>[orig_patent_app_number] => 085188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4036357 [patent_doc_number] => 05968129 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Method and apparatus for selectively retrieving information from a source computer using a terrestrial or satellite interface' [patent_app_type] => 1 [patent_app_number] => 9/082626 [patent_app_country] => US [patent_app_date] => 1998-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 9954 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968129.pdf [firstpage_image] =>[orig_patent_app_number] => 082626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3970741 [patent_doc_number] => 05999990 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Communicator having reconfigurable resources' [patent_app_type] => 1 [patent_app_number] => 9/080113 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5851 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999990.pdf [firstpage_image] =>[orig_patent_app_number] => 080113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3955038 [patent_doc_number] => 05930481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'System for concurrent cache data access by maintaining and selectively merging multiple ranked part copies' [patent_app_type] => 1 [patent_app_number] => 9/079491 [patent_app_country] => US [patent_app_date] => 1998-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6262 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930481.pdf [firstpage_image] =>[orig_patent_app_number] => 079491 [rel_patent_id] =>[rel_patent_doc_number] =>)