Daniel H. Pan

Array ( [id] => 4427277 [patent_doc_number] => 06226700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Computer system with bridge logic that includes an internal modular expansion bus and a common master interface for internal master devices' [patent_app_type] => 1 [patent_app_number] => 9/042173 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9018 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226700.pdf [firstpage_image] =>[orig_patent_app_number] => 042173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3915706 [patent_doc_number] => 05951647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Method and system for reconfiguring a communications stack' [patent_app_type] => 1 [patent_app_number] => 9/034600 [patent_app_country] => US [patent_app_date] => 1998-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7949 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951647.pdf [firstpage_image] =>[orig_patent_app_number] => 034600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4176473 [patent_doc_number] => 06105058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Communication control method and apparatus' [patent_app_type] => 1 [patent_app_number] => 9/027005 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 3594 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105058.pdf [firstpage_image] =>[orig_patent_app_number] => 027005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4211655 [patent_doc_number] => 06044454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'IEEE compliant floating point unit' [patent_app_type] => 1 [patent_app_number] => 9/026328 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2605 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044454.pdf [firstpage_image] =>[orig_patent_app_number] => 026328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4151807 [patent_doc_number] => 06035380 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/875936 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 8668 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035380.pdf [firstpage_image] =>[orig_patent_app_number] => 875936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3967667 [patent_doc_number] => 05983343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Data processing system having an apparatus for de-serialized status register operation and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/024927 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 11724 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983343.pdf [firstpage_image] =>[orig_patent_app_number] => 024927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4018501 [patent_doc_number] => 05924120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Method and apparatus for maximizing utilization of an internal processor bus in the context of external transactions running at speeds fractionally greater than internal transaction times' [patent_app_type] => 1 [patent_app_number] => 9/018320 [patent_app_country] => US [patent_app_date] => 1998-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3878 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/924/05924120.pdf [firstpage_image] =>[orig_patent_app_number] => 018320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4156202 [patent_doc_number] => 06122728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Technique for ordering internal processor register accesses' [patent_app_type] => 1 [patent_app_number] => 9/017297 [patent_app_country] => US [patent_app_date] => 1998-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6134 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122728.pdf [firstpage_image] =>[orig_patent_app_number] => 017297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3954971 [patent_doc_number] => 05930477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Header converting method' [patent_app_type] => 1 [patent_app_number] => 9/016380 [patent_app_country] => US [patent_app_date] => 1998-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 37 [patent_no_of_words] => 15437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930477.pdf [firstpage_image] =>[orig_patent_app_number] => 016380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4211148 [patent_doc_number] => 06044427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Upgradable mobile processor module and method for implementing same' [patent_app_type] => 1 [patent_app_number] => 9/015866 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2103 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044427.pdf [firstpage_image] =>[orig_patent_app_number] => 015866 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3993254 [patent_doc_number] => 05918062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Microprocessor including an efficient implemention of an accumulate instruction' [patent_app_type] => 1 [patent_app_number] => 9/014507 [patent_app_country] => US [patent_app_date] => 1998-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6967 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918062.pdf [firstpage_image] =>[orig_patent_app_number] => 014507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4179360 [patent_doc_number] => 06115803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Parallel computer which verifies direct data transmission between local memories with a send complete flag' [patent_app_type] => 1 [patent_app_number] => 9/010627 [patent_app_country] => US [patent_app_date] => 1998-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7233 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115803.pdf [firstpage_image] =>[orig_patent_app_number] => 010627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4024909 [patent_doc_number] => 06006291 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'High-throughput interface between a system memory controller and a peripheral device' [patent_app_type] => 1 [patent_app_number] => 9/002130 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 8853 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/006/06006291.pdf [firstpage_image] =>[orig_patent_app_number] => 002130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4412169 [patent_doc_number] => 06298410 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Apparatus and method for initiating hardware priority management by software controlled register access' [patent_app_type] => 1 [patent_app_number] => 9/001817 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4281 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298410.pdf [firstpage_image] =>[orig_patent_app_number] => 001817 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4195208 [patent_doc_number] => 06085309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Signal processing apparatus' [patent_app_type] => 1 [patent_app_number] => 9/001992 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 11986 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085309.pdf [firstpage_image] =>[orig_patent_app_number] => 001992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4132638 [patent_doc_number] => 06047322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Method and apparatus for quality of service management' [patent_app_type] => 1 [patent_app_number] => 8/999096 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047322.pdf [firstpage_image] =>[orig_patent_app_number] => 999096 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4100245 [patent_doc_number] => 06018746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'System and method for managing recovery information in a transaction processing system' [patent_app_type] => 1 [patent_app_number] => 8/996760 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7110 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018746.pdf [firstpage_image] =>[orig_patent_app_number] => 996760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4236667 [patent_doc_number] => 06041406 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Parallel and serial debug port on a processor' [patent_app_type] => 1 [patent_app_number] => 8/994518 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 11612 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041406.pdf [firstpage_image] =>[orig_patent_app_number] => 994518 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4133054 [patent_doc_number] => 06047351 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Jitter free instruction execution' [patent_app_type] => 1 [patent_app_number] => 8/989365 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5629 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047351.pdf [firstpage_image] =>[orig_patent_app_number] => 989365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4195222 [patent_doc_number] => 06085310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Method and apparatus for performing an operation multiple times in response to a single instruction' [patent_app_type] => 1 [patent_app_number] => 8/987290 [patent_app_country] => US [patent_app_date] => 1997-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 9 [patent_no_of_words] => 5244 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085310.pdf [firstpage_image] =>[orig_patent_app_number] => 987290 [rel_patent_id] =>[rel_patent_doc_number] =>)