Daniel H. Pan

Array ( [id] => 4042566 [patent_doc_number] => 05931939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Read crossbar elimination in a VLIW processor' [patent_app_type] => 1 [patent_app_number] => 8/909273 [patent_app_country] => US [patent_app_date] => 1997-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2612 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/931/05931939.pdf [firstpage_image] =>[orig_patent_app_number] => 909273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4052482 [patent_doc_number] => 05995725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method and apparatus for requesting and retrieving information from a source computer using terrestrial and satellite interfaces' [patent_app_type] => 1 [patent_app_number] => 8/901152 [patent_app_country] => US [patent_app_date] => 1997-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 6896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995725.pdf [firstpage_image] =>[orig_patent_app_number] => 901152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3877688 [patent_doc_number] => 05796955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Method for controlling the confirmation of association on an application layer of open systems interconnection between one communication equipment and a facing communication and a loop carrier system using the method' [patent_app_type] => 1 [patent_app_number] => 8/900044 [patent_app_country] => US [patent_app_date] => 1997-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 6654 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796955.pdf [firstpage_image] =>[orig_patent_app_number] => 900044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4037983 [patent_doc_number] => 05926645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Method and system for enabling multiple store instruction completions in a processing system' [patent_app_type] => 1 [patent_app_number] => 8/898359 [patent_app_country] => US [patent_app_date] => 1997-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5137 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926645.pdf [firstpage_image] =>[orig_patent_app_number] => 898359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3998615 [patent_doc_number] => 05862396 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Memory LSI with arithmetic logic processing capability, main memory system using the same, and method of controlling main memory system' [patent_app_type] => 1 [patent_app_number] => 8/897430 [patent_app_country] => US [patent_app_date] => 1997-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 9569 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862396.pdf [firstpage_image] =>[orig_patent_app_number] => 897430 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431462 [patent_doc_number] => 06519693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Method and system of program transmission optimization using a redundant transmission sequence' [patent_app_type] => B1 [patent_app_number] => 08/897900 [patent_app_country] => US [patent_app_date] => 1997-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 13481 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519693.pdf [firstpage_image] =>[orig_patent_app_number] => 08897900 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4040929 [patent_doc_number] => 05884090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Method and apparatus for partitioning an interconnection medium in a partitioned multiprocessor computer system' [patent_app_type] => 1 [patent_app_number] => 8/897237 [patent_app_country] => US [patent_app_date] => 1997-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 18729 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/884/05884090.pdf [firstpage_image] =>[orig_patent_app_number] => 897237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4254943 [patent_doc_number] => 06119198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Recursive address centrifuge for distributed memory massively parallel processing systems' [patent_app_type] => 1 [patent_app_number] => 8/889251 [patent_app_country] => US [patent_app_date] => 1997-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 12494 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119198.pdf [firstpage_image] =>[orig_patent_app_number] => 889251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4404232 [patent_doc_number] => 06263425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Circuit that implements semaphores in a multiprocessor environment without reliance on atomic test and set operations of the processor cores' [patent_app_type] => 1 [patent_app_number] => 8/889796 [patent_app_country] => US [patent_app_date] => 1997-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3236 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263425.pdf [firstpage_image] =>[orig_patent_app_number] => 889796 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3794269 [patent_doc_number] => 05809274 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Purge control for ON-chip cache memory' [patent_app_type] => 1 [patent_app_number] => 8/886464 [patent_app_country] => US [patent_app_date] => 1997-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 8315 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809274.pdf [firstpage_image] =>[orig_patent_app_number] => 886464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4239656 [patent_doc_number] => 06012094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Method of stratified transaction processing' [patent_app_type] => 1 [patent_app_number] => 8/884954 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7243 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012094.pdf [firstpage_image] =>[orig_patent_app_number] => 884954 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4008712 [patent_doc_number] => 05892966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Processor complex for executing multimedia functions' [patent_app_type] => 1 [patent_app_number] => 8/884257 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8520 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892966.pdf [firstpage_image] =>[orig_patent_app_number] => 884257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3970197 [patent_doc_number] => 05958047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Method for precise architectural update in an out-of-order processor' [patent_app_type] => 1 [patent_app_number] => 8/881730 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6425 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958047.pdf [firstpage_image] =>[orig_patent_app_number] => 881730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4082076 [patent_doc_number] => 05867724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Integrated routing and shifting circuit and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/865663 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867724.pdf [firstpage_image] =>[orig_patent_app_number] => 865663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3871839 [patent_doc_number] => 05768525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Transparent support of protocol and data compression features for data communication' [patent_app_type] => 1 [patent_app_number] => 8/845323 [patent_app_country] => US [patent_app_date] => 1997-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5800 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768525.pdf [firstpage_image] =>[orig_patent_app_number] => 845323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4423483 [patent_doc_number] => 06311263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Data processing circuits and interfaces' [patent_app_type] => 1 [patent_app_number] => 8/809498 [patent_app_country] => US [patent_app_date] => 1997-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 13834 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311263.pdf [firstpage_image] =>[orig_patent_app_number] => 809498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4022287 [patent_doc_number] => 05987590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'PC circuits, systems and methods' [patent_app_type] => 1 [patent_app_number] => 8/823257 [patent_app_country] => US [patent_app_date] => 1997-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 64 [patent_no_of_words] => 16867 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987590.pdf [firstpage_image] =>[orig_patent_app_number] => 823257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3974731 [patent_doc_number] => 05901330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'In-circuit programming architecture with ROM and flash memory' [patent_app_type] => 1 [patent_app_number] => 8/818389 [patent_app_country] => US [patent_app_date] => 1997-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6489 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901330.pdf [firstpage_image] =>[orig_patent_app_number] => 818389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4008007 [patent_doc_number] => 05892918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Block transfer method for use with parallel computer system' [patent_app_type] => 1 [patent_app_number] => 8/815089 [patent_app_country] => US [patent_app_date] => 1997-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5503 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 26 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892918.pdf [firstpage_image] =>[orig_patent_app_number] => 815089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3758482 [patent_doc_number] => 05754813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Data processor' [patent_app_type] => 1 [patent_app_number] => 8/811663 [patent_app_country] => US [patent_app_date] => 1997-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7563 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754813.pdf [firstpage_image] =>[orig_patent_app_number] => 811663 [rel_patent_id] =>[rel_patent_doc_number] =>)