Search

Daniel H. Pan

Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2302, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3700005 [patent_doc_number] => 05664063 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Automatic user notification of certain meeting attributes of a posted calendar event' [patent_app_type] => 1 [patent_app_number] => 8/347626 [patent_app_country] => US [patent_app_date] => 1994-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2806 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/664/05664063.pdf [firstpage_image] =>[orig_patent_app_number] => 347626 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/347626
Automatic user notification of certain meeting attributes of a posted calendar event Nov 30, 1994 Issued
Array ( [id] => 3668157 [patent_doc_number] => 05623685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Vector register validity indication to handle out-of-order element arrival for a vector computer with variable memory latency' [patent_app_type] => 1 [patent_app_number] => 8/347953 [patent_app_country] => US [patent_app_date] => 1994-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9157 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623685.pdf [firstpage_image] =>[orig_patent_app_number] => 347953 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/347953
Vector register validity indication to handle out-of-order element arrival for a vector computer with variable memory latency Nov 30, 1994 Issued
Array ( [id] => 3672526 [patent_doc_number] => 05649107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Traffic statistics processing apparatus using memory to increase speed and capacity by storing partially manipulated data' [patent_app_type] => 1 [patent_app_number] => 8/346079 [patent_app_country] => US [patent_app_date] => 1994-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3208 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649107.pdf [firstpage_image] =>[orig_patent_app_number] => 346079 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/346079
Traffic statistics processing apparatus using memory to increase speed and capacity by storing partially manipulated data Nov 28, 1994 Issued
Array ( [id] => 3661871 [patent_doc_number] => 05606709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Register group circuit for data processing system' [patent_app_type] => 1 [patent_app_number] => 8/344365 [patent_app_country] => US [patent_app_date] => 1994-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 6455 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606709.pdf [firstpage_image] =>[orig_patent_app_number] => 344365 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/344365
Register group circuit for data processing system Nov 22, 1994 Issued
Array ( [id] => 3900736 [patent_doc_number] => 05715403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'System for controlling the distribution and use of digital works having attached usage rights where the usage rights are defined by a usage rights grammar' [patent_app_type] => 1 [patent_app_number] => 8/344041 [patent_app_country] => US [patent_app_date] => 1994-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 29249 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715403.pdf [firstpage_image] =>[orig_patent_app_number] => 344041 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/344041
System for controlling the distribution and use of digital works having attached usage rights where the usage rights are defined by a usage rights grammar Nov 22, 1994 Issued
Array ( [id] => 3513117 [patent_doc_number] => 05570085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-29 [patent_title] => 'Programmable distributed appliance control system' [patent_app_type] => 1 [patent_app_number] => 8/343612 [patent_app_country] => US [patent_app_date] => 1994-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7284 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/570/05570085.pdf [firstpage_image] =>[orig_patent_app_number] => 343612 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/343612
Programmable distributed appliance control system Nov 21, 1994 Issued
Array ( [id] => 3707879 [patent_doc_number] => 05680584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Simulator system for code execution and debugging within a multi-architecture environment' [patent_app_type] => 1 [patent_app_number] => 8/342668 [patent_app_country] => US [patent_app_date] => 1994-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4959 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680584.pdf [firstpage_image] =>[orig_patent_app_number] => 342668 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/342668
Simulator system for code execution and debugging within a multi-architecture environment Nov 20, 1994 Issued
Array ( [id] => 3567036 [patent_doc_number] => 05574934 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Preemptive priority-based transmission of signals using virtual channels' [patent_app_type] => 1 [patent_app_number] => 8/340173 [patent_app_country] => US [patent_app_date] => 1994-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 52381 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574934.pdf [firstpage_image] =>[orig_patent_app_number] => 340173 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/340173
Preemptive priority-based transmission of signals using virtual channels Nov 14, 1994 Issued
Array ( [id] => 3563267 [patent_doc_number] => 05548798 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Method and apparatus for solving dense systems of linear equations with an iterative method that employs partial multiplications using rank compressed SVD basis matrices of the partitioned submatrices of the coefficient matrix' [patent_app_type] => 1 [patent_app_number] => 8/337246 [patent_app_country] => US [patent_app_date] => 1994-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4748 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548798.pdf [firstpage_image] =>[orig_patent_app_number] => 337246 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/337246
Method and apparatus for solving dense systems of linear equations with an iterative method that employs partial multiplications using rank compressed SVD basis matrices of the partitioned submatrices of the coefficient matrix Nov 9, 1994 Issued
08/333521 A METHOD FOR CONTROLLING THE CONFIRMATION OF ASSOCIATION ON AN APPLICATION LAYER OF OPEN SYSTEMS INTERCONNECTION BETWEEN ONE COMMUNICATION EQUIPMENT AND A FACING COMMUNICATION AND A LOOP CARRIER SYSTEM USING THE METHOD Nov 1, 1994 Abandoned
Array ( [id] => 3603340 [patent_doc_number] => 05586269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Communication control device and method for automatically determining a self-address' [patent_app_type] => 1 [patent_app_number] => 8/333579 [patent_app_country] => US [patent_app_date] => 1994-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4775 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586269.pdf [firstpage_image] =>[orig_patent_app_number] => 333579 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/333579
Communication control device and method for automatically determining a self-address Nov 1, 1994 Issued
Array ( [id] => 3660874 [patent_doc_number] => 05630153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Integrated digital signal processor/general purpose CPU with shared internal memory' [patent_app_type] => 1 [patent_app_number] => 8/317783 [patent_app_country] => US [patent_app_date] => 1994-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5318 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/630/05630153.pdf [firstpage_image] =>[orig_patent_app_number] => 317783 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/317783
Integrated digital signal processor/general purpose CPU with shared internal memory Oct 3, 1994 Issued
Array ( [id] => 3661857 [patent_doc_number] => 05606707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Real-time image processor' [patent_app_type] => 1 [patent_app_number] => 8/312926 [patent_app_country] => US [patent_app_date] => 1994-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 24843 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606707.pdf [firstpage_image] =>[orig_patent_app_number] => 312926 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/312926
Real-time image processor Sep 29, 1994 Issued
Array ( [id] => 3671030 [patent_doc_number] => 05659782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'System and method for handling load and/or store operations in a superscalar microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/307042 [patent_app_country] => US [patent_app_date] => 1994-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10731 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659782.pdf [firstpage_image] =>[orig_patent_app_number] => 307042 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/307042
System and method for handling load and/or store operations in a superscalar microprocessor Sep 15, 1994 Issued
Array ( [id] => 3708302 [patent_doc_number] => 05596764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Debug mechanism for parallel-operating DSP module and CPU core' [patent_app_type] => 1 [patent_app_number] => 8/307385 [patent_app_country] => US [patent_app_date] => 1994-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 51 [patent_no_of_words] => 23415 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596764.pdf [firstpage_image] =>[orig_patent_app_number] => 307385 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/307385
Debug mechanism for parallel-operating DSP module and CPU core Sep 13, 1994 Issued
Array ( [id] => 4345391 [patent_doc_number] => 06330583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Computer network of interactive multitasking computers for parallel processing of network subtasks concurrently with local tasks' [patent_app_type] => 1 [patent_app_number] => 8/303763 [patent_app_country] => US [patent_app_date] => 1994-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3113 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330583.pdf [firstpage_image] =>[orig_patent_app_number] => 303763 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/303763
Computer network of interactive multitasking computers for parallel processing of network subtasks concurrently with local tasks Sep 8, 1994 Issued
Array ( [id] => 3556051 [patent_doc_number] => 05555374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'System and method for coupling a plurality of peripheral devices to a host computer through a host computer parallel port' [patent_app_type] => 1 [patent_app_number] => 8/296713 [patent_app_country] => US [patent_app_date] => 1994-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8228 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/555/05555374.pdf [firstpage_image] =>[orig_patent_app_number] => 296713 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/296713
System and method for coupling a plurality of peripheral devices to a host computer through a host computer parallel port Aug 25, 1994 Issued
Array ( [id] => 3670885 [patent_doc_number] => 05627970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Methods and apparatus for achieving and maintaining optimum transmission rates and preventing data loss in a processing system nework' [patent_app_type] => 1 [patent_app_number] => 8/287018 [patent_app_country] => US [patent_app_date] => 1994-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4822 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627970.pdf [firstpage_image] =>[orig_patent_app_number] => 287018 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/287018
Methods and apparatus for achieving and maintaining optimum transmission rates and preventing data loss in a processing system nework Aug 7, 1994 Issued
Array ( [id] => 3503147 [patent_doc_number] => 05561772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'Expansion bus system for replicating an internal bus as an external bus with logical interrupts replacing physical interrupt lines' [patent_app_type] => 1 [patent_app_number] => 8/280924 [patent_app_country] => US [patent_app_date] => 1994-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 7933 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/561/05561772.pdf [firstpage_image] =>[orig_patent_app_number] => 280924 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/280924
Expansion bus system for replicating an internal bus as an external bus with logical interrupts replacing physical interrupt lines Jul 25, 1994 Issued
Array ( [id] => 3595915 [patent_doc_number] => 05581739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Two lane computing systems' [patent_app_type] => 1 [patent_app_number] => 8/280511 [patent_app_country] => US [patent_app_date] => 1994-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3782 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581739.pdf [firstpage_image] =>[orig_patent_app_number] => 280511 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/280511
Two lane computing systems Jul 25, 1994 Issued
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