Search

Daniel H. Pan

Examiner (ID: 18277)

Most Active Art Unit
2182
Art Unit(s)
2302, 2182, 2183, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1279
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16217168 [patent_doc_number] => 10732980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Apparatus and method for controlling use of a register cache [patent_app_type] => utility [patent_app_number] => 16/018492 [patent_app_country] => US [patent_app_date] => 2018-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 12834 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16018492 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/018492
Apparatus and method for controlling use of a register cache Jun 25, 2018 Issued
Array ( [id] => 13483069 [patent_doc_number] => 20180293077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => OPERATION OF A MULTI-SLICE PROCESSOR WITH AN EXPANDED MERGE FETCHING QUEUE [patent_app_type] => utility [patent_app_number] => 16/003950 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16003950 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/003950
Operation of a multi-slice processor with an expanded merge fetching queue Jun 7, 2018 Issued
Array ( [id] => 13448901 [patent_doc_number] => 20180275993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => POWER MANAGEMENT OF BRANCH PREDICTORS IN A COMPUTER PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/995682 [patent_app_country] => US [patent_app_date] => 2018-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6404 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15995682 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/995682
Power management of branch predictors in a computer processor May 31, 2018 Issued
Array ( [id] => 15854673 [patent_doc_number] => 10642620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Computation engine with strided dot product [patent_app_type] => utility [patent_app_number] => 15/946724 [patent_app_country] => US [patent_app_date] => 2018-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5536 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15946724 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/946724
Computation engine with strided dot product Apr 4, 2018 Issued
Array ( [id] => 17076823 [patent_doc_number] => 11113223 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-07 [patent_title] => Dual mode interconnect [patent_app_type] => utility [patent_app_number] => 15/944490 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 12418 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15944490 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/944490
Dual mode interconnect Apr 2, 2018 Issued
Array ( [id] => 16248172 [patent_doc_number] => 10747531 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-18 [patent_title] => Core for a data processing engine in an integrated circuit [patent_app_type] => utility [patent_app_number] => 15/944315 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15944315 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/944315
Core for a data processing engine in an integrated circuit Apr 2, 2018 Issued
Array ( [id] => 13906089 [patent_doc_number] => 20190042249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => HARDWARE ACCELERATORS AND METHODS FOR HIGH-PERFORMANCE AUTHENTICATED ENCRYPTION [patent_app_type] => utility [patent_app_number] => 15/943654 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943654 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943654
Hardware accelerators and methods for high-performance authenticated encryption Apr 1, 2018 Issued
Array ( [id] => 15952759 [patent_doc_number] => 10664287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Systems and methods for implementing chained tile operations [patent_app_type] => utility [patent_app_number] => 15/942201 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 50 [patent_no_of_words] => 31023 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15942201 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/942201
Systems and methods for implementing chained tile operations Mar 29, 2018 Issued
Array ( [id] => 15886855 [patent_doc_number] => 10649772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Method and apparatus for efficient matrix transpose [patent_app_type] => utility [patent_app_number] => 15/941526 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 19087 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15941526 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/941526
Method and apparatus for efficient matrix transpose Mar 29, 2018 Issued
Array ( [id] => 14935045 [patent_doc_number] => 20190303160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => BRANCH TARGET ADDRESS PROVISION [patent_app_type] => utility [patent_app_number] => 15/939722 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15939722 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/939722
Branch target address provision Mar 28, 2018 Issued
Array ( [id] => 14935011 [patent_doc_number] => 20190303143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => Dynamic Acceleration of Data Processor Operations Using Data-flow Analysis [patent_app_type] => utility [patent_app_number] => 15/939637 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15939637 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/939637
Dynamic acceleration of data processor operations using data-flow analysis Mar 28, 2018 Issued
Array ( [id] => 14539021 [patent_doc_number] => 20190205132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => LOOK UP TABLE WITH DATA ELEMENT PROMOTION [patent_app_type] => utility [patent_app_number] => 15/940283 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15940283 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/940283
Look up table with data element promotion Mar 28, 2018 Issued
Array ( [id] => 15886875 [patent_doc_number] => 10649782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Apparatus and method for controlling branch prediction [patent_app_type] => utility [patent_app_number] => 15/939827 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 11437 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15939827 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/939827
Apparatus and method for controlling branch prediction Mar 28, 2018 Issued
Array ( [id] => 13515837 [patent_doc_number] => 20180309461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => APPARATUS AND METHOD FOR VECTOR COMPRESSION [patent_app_type] => utility [patent_app_number] => 15/922642 [patent_app_country] => US [patent_app_date] => 2018-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15922642 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/922642
Apparatus and method for vector compression Mar 14, 2018 Issued
Array ( [id] => 13579861 [patent_doc_number] => 20180341479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => ACCESSING DATA IN MULTI-DIMENSIONAL TENSORS USING ADDERS [patent_app_type] => utility [patent_app_number] => 15/903991 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15903991 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/903991
Accessing data in multi-dimensional tensors using adders Feb 22, 2018 Issued
Array ( [id] => 15638613 [patent_doc_number] => 10592300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization [patent_app_type] => utility [patent_app_number] => 15/896881 [patent_app_country] => US [patent_app_date] => 2018-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13406 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15896881 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/896881
Method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization Feb 13, 2018 Issued
Array ( [id] => 13361399 [patent_doc_number] => 20180232239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => OPTIMIZE CONTROL-FLOW CONVERGENCE ON SIMD ENGINE USING DIVERGENCE DEPTH [patent_app_type] => utility [patent_app_number] => 15/890548 [patent_app_country] => US [patent_app_date] => 2018-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15890548 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/890548
Optimize control-flow convergence on SIMD engine using divergence depth Feb 6, 2018 Issued
Array ( [id] => 14629171 [patent_doc_number] => 20190227953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => REAL TIME STACK PROTECTION [patent_app_type] => utility [patent_app_number] => 15/876500 [patent_app_country] => US [patent_app_date] => 2018-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15876500 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/876500
Real time stack protection Jan 21, 2018 Issued
Array ( [id] => 13347431 [patent_doc_number] => 20180225255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => HARDWARE PROCESSORS AND METHODS FOR TIGHTLY-COUPLED HETEROGENEOUS COMPUTING [patent_app_type] => utility [patent_app_number] => 15/870632 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15870632 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/870632
Hardware processors and methods for tightly-coupled heterogeneous computing Jan 11, 2018 Issued
Array ( [id] => 13347167 [patent_doc_number] => 20180225123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => METHOD FOR POPULATING AND INSTRUCTION VIEW DATA STRUCTURE BY USING REGISTER TEMPLATE SNAPSHOTS [patent_app_type] => utility [patent_app_number] => 15/866323 [patent_app_country] => US [patent_app_date] => 2018-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9632 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15866323 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/866323
METHOD FOR POPULATING AND INSTRUCTION VIEW DATA STRUCTURE BY USING REGISTER TEMPLATE SNAPSHOTS Jan 8, 2018 Abandoned
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