Search

Daniel H. Pan

Examiner (ID: 721, Phone: (571)272-4172 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2302, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1281
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3473810 [patent_doc_number] => 05392444 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Programmable controller for completing the execution of a block of user programs within a set time period' [patent_app_type] => 1 [patent_app_number] => 8/024865 [patent_app_country] => US [patent_app_date] => 1993-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 2801 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392444.pdf [firstpage_image] =>[orig_patent_app_number] => 024865 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/024865
Programmable controller for completing the execution of a block of user programs within a set time period Feb 25, 1993 Issued
Array ( [id] => 3042030 [patent_doc_number] => 05349690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Fair arbitration scheme for arbitrating between multiple nodes in a computer system seeking control of a common bus' [patent_app_type] => 1 [patent_app_number] => 8/016419 [patent_app_country] => US [patent_app_date] => 1993-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1880 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/349/05349690.pdf [firstpage_image] =>[orig_patent_app_number] => 016419 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/016419
Fair arbitration scheme for arbitrating between multiple nodes in a computer system seeking control of a common bus Feb 10, 1993 Issued
Array ( [id] => 3603216 [patent_doc_number] => 05586263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'High speed data communication control device having an uncompetitive bus construction' [patent_app_type] => 1 [patent_app_number] => 8/013212 [patent_app_country] => US [patent_app_date] => 1993-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3232 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586263.pdf [firstpage_image] =>[orig_patent_app_number] => 013212 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/013212
High speed data communication control device having an uncompetitive bus construction Jan 31, 1993 Issued
08/011102 INTEGRATED DIGITAL SIGNAL PROCESSOR/GENERAL PURPOSE CPU WITH SHARED INTERNAL MEMORY Jan 28, 1993 Abandoned
Array ( [id] => 3133768 [patent_doc_number] => 05450605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-12 [patent_title] => 'Boundary markers for indicating the boundary of a variable length instruction to facilitate parallel processing of sequential instructions' [patent_app_type] => 1 [patent_app_number] => 8/010360 [patent_app_country] => US [patent_app_date] => 1993-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5637 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/450/05450605.pdf [firstpage_image] =>[orig_patent_app_number] => 010360 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/010360
Boundary markers for indicating the boundary of a variable length instruction to facilitate parallel processing of sequential instructions Jan 27, 1993 Issued
08/008981 DIGITAL IMAGE PROCESSING DEVICE FOR ENLARGING OR REDUCING AN ORIGINAL IMAGE Jan 25, 1993 Abandoned
Array ( [id] => 3674286 [patent_doc_number] => 05649224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Integrated circuit card having contacts along the side rails and method for transferring information using the contacts' [patent_app_type] => 1 [patent_app_number] => 8/009135 [patent_app_country] => US [patent_app_date] => 1993-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5291 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649224.pdf [firstpage_image] =>[orig_patent_app_number] => 009135 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/009135
Integrated circuit card having contacts along the side rails and method for transferring information using the contacts Jan 25, 1993 Issued
08/007582 A METHOD AND APPARATUS FOR EXECUTNG AN INSTRUCTION WITH MULTIPLE BRANCHING OPTIONS IN ONE CYCLE Jan 21, 1993 Abandoned
Array ( [id] => 3129841 [patent_doc_number] => 05410722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Queue system for dynamically allocating and moving memory registers between a plurality of pseudo queues' [patent_app_type] => 1 [patent_app_number] => 8/007199 [patent_app_country] => US [patent_app_date] => 1993-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 6045 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 404 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/410/05410722.pdf [firstpage_image] =>[orig_patent_app_number] => 007199 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/007199
Queue system for dynamically allocating and moving memory registers between a plurality of pseudo queues Jan 20, 1993 Issued
Array ( [id] => 3589413 [patent_doc_number] => 05524257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Method of parallel processing for inference and a system therefor' [patent_app_type] => 1 [patent_app_number] => 8/005591 [patent_app_country] => US [patent_app_date] => 1993-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3766 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/524/05524257.pdf [firstpage_image] =>[orig_patent_app_number] => 005591 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/005591
Method of parallel processing for inference and a system therefor Jan 18, 1993 Issued
Array ( [id] => 3849757 [patent_doc_number] => 05761473 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Method and system for increased instruction synchronization efficiency in a superscalar processsor system utilizing partial data dependency interlocking' [patent_app_type] => 1 [patent_app_number] => 8/001863 [patent_app_country] => US [patent_app_date] => 1993-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2403 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761473.pdf [firstpage_image] =>[orig_patent_app_number] => 001863 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/001863
Method and system for increased instruction synchronization efficiency in a superscalar processsor system utilizing partial data dependency interlocking Jan 7, 1993 Issued
Array ( [id] => 3458604 [patent_doc_number] => 05421020 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Counter register implementation for speculative execution of branch on count instructions' [patent_app_type] => 1 [patent_app_number] => 8/002445 [patent_app_country] => US [patent_app_date] => 1993-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3190 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/421/05421020.pdf [firstpage_image] =>[orig_patent_app_number] => 002445 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/002445
Counter register implementation for speculative execution of branch on count instructions Jan 7, 1993 Issued
Array ( [id] => 3691339 [patent_doc_number] => 05691493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Multi-channel tone generation apparatus with multiple CPU\'s executing programs in parallel' [patent_app_type] => 1 [patent_app_number] => 8/001184 [patent_app_country] => US [patent_app_date] => 1993-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 66 [patent_no_of_words] => 34983 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691493.pdf [firstpage_image] =>[orig_patent_app_number] => 001184 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/001184
Multi-channel tone generation apparatus with multiple CPU's executing programs in parallel Jan 6, 1993 Issued
Array ( [id] => 3673144 [patent_doc_number] => 05592675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Computer controlled method and system capable of preserving information representing plural work states and recovering the work states' [patent_app_type] => 1 [patent_app_number] => 8/001248 [patent_app_country] => US [patent_app_date] => 1993-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 11727 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592675.pdf [firstpage_image] =>[orig_patent_app_number] => 001248 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/001248
Computer controlled method and system capable of preserving information representing plural work states and recovering the work states Jan 5, 1993 Issued
Array ( [id] => 3123183 [patent_doc_number] => 05465372 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-07 [patent_title] => 'Dataflow computer for following data dependent path processes' [patent_app_type] => 1 [patent_app_number] => 8/000994 [patent_app_country] => US [patent_app_date] => 1993-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8590 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/465/05465372.pdf [firstpage_image] =>[orig_patent_app_number] => 000994 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/000994
Dataflow computer for following data dependent path processes Jan 5, 1993 Issued
Array ( [id] => 3439627 [patent_doc_number] => 05455956 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Connection tree rearrangement method and system for rearrangebly-blocked DSM networks' [patent_app_type] => 1 [patent_app_number] => 7/999288 [patent_app_country] => US [patent_app_date] => 1992-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 11661 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455956.pdf [firstpage_image] =>[orig_patent_app_number] => 999288 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/999288
Connection tree rearrangement method and system for rearrangebly-blocked DSM networks Dec 29, 1992 Issued
Array ( [id] => 3428415 [patent_doc_number] => 05394557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'State machine operating in multiple parallel phase and method thereof' [patent_app_type] => 1 [patent_app_number] => 7/998795 [patent_app_country] => US [patent_app_date] => 1992-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7687 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/394/05394557.pdf [firstpage_image] =>[orig_patent_app_number] => 998795 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/998795
State machine operating in multiple parallel phase and method thereof Dec 29, 1992 Issued
07/997219 A PIPELINED DATA PROCESSING DEVICE HAVING IMPROVED HARDWARE CONTROL OVER AN ARITHMETIC OPERATIONS UNIT Dec 27, 1992 Abandoned
Array ( [id] => 3634578 [patent_doc_number] => 05689692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Method and apparatus for decoding an encoded NRZ signal' [patent_app_type] => 1 [patent_app_number] => 7/996224 [patent_app_country] => US [patent_app_date] => 1992-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4190 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689692.pdf [firstpage_image] =>[orig_patent_app_number] => 996224 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/996224
Method and apparatus for decoding an encoded NRZ signal Dec 22, 1992 Issued
Array ( [id] => 3028279 [patent_doc_number] => 05341482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Method for synchronization of arithmetic exceptions in central processing units having pipelined execution units simultaneously executing instructions' [patent_app_type] => 1 [patent_app_number] => 7/995341 [patent_app_country] => US [patent_app_date] => 1992-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4156 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341482.pdf [firstpage_image] =>[orig_patent_app_number] => 995341 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/995341
Method for synchronization of arithmetic exceptions in central processing units having pipelined execution units simultaneously executing instructions Dec 21, 1992 Issued
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