Search

Daniel H. Pan

Examiner (ID: 18277)

Most Active Art Unit
2182
Art Unit(s)
2302, 2182, 2183, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1279
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14570805 [patent_doc_number] => 20190213009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => CHECKPOINTING OF ARCHITECTURAL STATE FOR IN ORDER PROCESSING CIRCUITRY [patent_app_type] => utility [patent_app_number] => 15/862728 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8976 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15862728 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/862728
Checkpointing of architectural state for in order processing circuitry Jan 4, 2018 Issued
Array ( [id] => 12646974 [patent_doc_number] => 20180107489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => COMPUTER INSTRUCTION PROCESSING METHOD, COPROCESSOR, AND SYSTEM [patent_app_type] => utility [patent_app_number] => 15/844191 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21549 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15844191 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/844191
Computer instruction processing method, coprocessor, and system Dec 14, 2017 Issued
Array ( [id] => 14034393 [patent_doc_number] => 10228947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Accessing data in multi-dimensional tensors [patent_app_type] => utility [patent_app_number] => 15/844192 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15844192 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/844192
Accessing data in multi-dimensional tensors Dec 14, 2017 Issued
Array ( [id] => 14161851 [patent_doc_number] => 20190108028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => EXECUTING LOAD-STORE OPERATIONS WITHOUT ADDRESS TRANSLATION HARDWARE PER LOAD-STORE UNIT PORT [patent_app_type] => utility [patent_app_number] => 15/825625 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825625 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825625
Executing load-store operations without address translation hardware per load-store unit port Nov 28, 2017 Issued
Array ( [id] => 15167321 [patent_doc_number] => 10489154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Apparatus and method for complex multiply and accumulate [patent_app_type] => utility [patent_app_number] => 15/824324 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 16999 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824324 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824324
Apparatus and method for complex multiply and accumulate Nov 27, 2017 Issued
Array ( [id] => 14379137 [patent_doc_number] => 20190163481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => EXECUTING PROCESSOR INSTRUCTIONS USING MINIMAL DEPENDENCY QUEUE [patent_app_type] => utility [patent_app_number] => 15/823632 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15823632 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/823632
Executing processor instructions using minimal dependency queue Nov 27, 2017 Issued
Array ( [id] => 14379123 [patent_doc_number] => 20190163474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => APPARATUS AND METHOD FOR CONVERTING A FLOATING-POINT VALUE FROM HALF PRECISION TO SINGLE PRECISION [patent_app_type] => utility [patent_app_number] => 15/824339 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824339 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824339
Apparatus and method for converting a floating-point value from half precision to single precision Nov 27, 2017 Issued
Array ( [id] => 14379121 [patent_doc_number] => 20190163473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => APPARATUS AND METHOD FOR COMPLEX MULTIPLICATION [patent_app_type] => utility [patent_app_number] => 15/824333 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16695 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824333 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824333
Apparatus and method for complex multiplication Nov 27, 2017 Issued
Array ( [id] => 14379131 [patent_doc_number] => 20190163478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => SYNCHRONIZING A SET OF CODE BRANCHES [patent_app_type] => utility [patent_app_number] => 15/822481 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15822481 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/822481
Synchronizing a set of code branches Nov 26, 2017 Issued
Array ( [id] => 14379125 [patent_doc_number] => 20190163475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => SYSTEM AND METHOD FOR STORE FUSION [patent_app_type] => utility [patent_app_number] => 15/822515 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15822515 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/822515
System and method for store fusion Nov 26, 2017 Issued
Array ( [id] => 13417371 [patent_doc_number] => 20180260228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => SPIN LOOP DELAY INSTRUCTION [patent_app_type] => utility [patent_app_number] => 15/810826 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/810826
Spin loop delay instruction Nov 12, 2017 Issued
Array ( [id] => 12234882 [patent_doc_number] => 20180067744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'NON-DEFAULT INSTRUCTION HANDLING WITHIN TRANSACTION' [patent_app_type] => utility [patent_app_number] => 15/807613 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 18001 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15807613 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/807613
Non-default instruction handling within transaction Nov 8, 2017 Issued
Array ( [id] => 12234884 [patent_doc_number] => 20180067747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'DYNAMIC THREAD SHARING IN BRANCH PREDICTION STRUCTURES' [patent_app_type] => utility [patent_app_number] => 15/808398 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7021 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15808398 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/808398
Dynamic thread sharing in branch prediction structures Nov 8, 2017 Issued
Array ( [id] => 12611781 [patent_doc_number] => 20180095757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => DECIMAL LOAD IMMEDIATE INSTRUCTION [patent_app_type] => utility [patent_app_number] => 15/806816 [patent_app_country] => US [patent_app_date] => 2017-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15806816 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/806816
Decimal load immediate instruction Nov 7, 2017 Issued
Array ( [id] => 12180562 [patent_doc_number] => 20180039498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'METHOD FOR A DELAYED BRANCH IMPLEMENTATION BY USING A FRONT END TRACK TABLE' [patent_app_type] => utility [patent_app_number] => 15/783923 [patent_app_country] => US [patent_app_date] => 2017-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4966 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15783923 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/783923
Method for a delayed branch implementation by using a front end track table Oct 12, 2017 Issued
Array ( [id] => 14394531 [patent_doc_number] => 10310546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Arbitrary waveform generator based on instruction architecture [patent_app_type] => utility [patent_app_number] => 15/730407 [patent_app_country] => US [patent_app_date] => 2017-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4548 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 531 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15730407 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/730407
Arbitrary waveform generator based on instruction architecture Oct 10, 2017 Issued
Array ( [id] => 15578013 [patent_doc_number] => 10579387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processor [patent_app_type] => utility [patent_app_number] => 15/726575 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16706 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726575 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726575
Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processor Oct 5, 2017 Issued
Array ( [id] => 15386863 [patent_doc_number] => 10534616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Load-hit-load detection in an out-of-order processor [patent_app_type] => utility [patent_app_number] => 15/726563 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17351 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726563 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726563
Load-hit-load detection in an out-of-order processor Oct 5, 2017 Issued
Array ( [id] => 14161843 [patent_doc_number] => 20190108024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => EXECUTING LOAD-STORE OPERATIONS WITHOUT ADDRESS TRANSLATION HARDWARE PER LOAD-STORE UNIT PORT [patent_app_type] => utility [patent_app_number] => 15/726639 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726639 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726639
Executing load-store operations without address translation hardware per load-store unit port Oct 5, 2017 Issued
Array ( [id] => 14161863 [patent_doc_number] => 20190108034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => HAZARD DETECTION OF OUT-OF-ORDER EXECUTION OF LOAD AND STORE INSTRUCTIONS IN PROCESSORS WITHOUT USING REAL ADDRESSES [patent_app_type] => utility [patent_app_number] => 15/726538 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726538 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726538
Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses Oct 5, 2017 Issued
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