| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2761881
[patent_doc_number] => 05072364
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-10
[patent_title] => 'Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel'
[patent_app_type] => 1
[patent_app_number] => 7/356316
[patent_app_country] => US
[patent_app_date] => 1989-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
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[pdf_file] => patents/05/072/05072364.pdf
[firstpage_image] =>[orig_patent_app_number] => 356316
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/356316 | Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel | May 23, 1989 | Issued |
Array
(
[id] => 2863918
[patent_doc_number] => 05134692
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-07-28
[patent_title] => 'Combined electronic calculator and abacus with deflective guide bars'
[patent_app_type] => 1
[patent_app_number] => 7/355770
[patent_app_country] => US
[patent_app_date] => 1989-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 1961
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/134/05134692.pdf
[firstpage_image] =>[orig_patent_app_number] => 355770
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/355770 | Combined electronic calculator and abacus with deflective guide bars | May 22, 1989 | Issued |
Array
(
[id] => 2843299
[patent_doc_number] => 05175851
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-29
[patent_title] => 'System and method for controlling client machine access to a portion of a file with a variable length'
[patent_app_type] => 1
[patent_app_number] => 7/352084
[patent_app_country] => US
[patent_app_date] => 1989-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 8623
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 199
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/175/05175851.pdf
[firstpage_image] =>[orig_patent_app_number] => 352084
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/352084 | System and method for controlling client machine access to a portion of a file with a variable length | May 14, 1989 | Issued |
| 07/347967 | A DATA PROCESSING DEVICE FOR EXECUTING CONDITIONAL INSTRUCTIONS BASED ON STSTUS AND MASK BITS | May 3, 1989 | Abandoned |
Array
(
[id] => 2998953
[patent_doc_number] => 05212798
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-18
[patent_title] => 'Floppy disk drive apparatus with variable rotation disk speeds and varible stopping periods'
[patent_app_type] => 1
[patent_app_number] => 7/377823
[patent_app_country] => US
[patent_app_date] => 1989-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1910
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/212/05212798.pdf
[firstpage_image] =>[orig_patent_app_number] => 377823
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/377823 | Floppy disk drive apparatus with variable rotation disk speeds and varible stopping periods | Apr 27, 1989 | Issued |
| 07/343384 | DATA PROCESSOR FOR PROCESSING DATA OR AN ARRAY OF DATA WITHOUT INCREASING A NUMBER OF BITS | Apr 25, 1989 | Abandoned |
Array
(
[id] => 2799347
[patent_doc_number] => 05155831
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-13
[patent_title] => 'Data processing system with fast queue store interposed between store-through caches and a main memory'
[patent_app_type] => 1
[patent_app_number] => 7/342493
[patent_app_country] => US
[patent_app_date] => 1989-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4098
[patent_no_of_claims] => 11
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[patent_words_short_claim] => 271
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/155/05155831.pdf
[firstpage_image] =>[orig_patent_app_number] => 342493
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/342493 | Data processing system with fast queue store interposed between store-through caches and a main memory | Apr 23, 1989 | Issued |
| 07/339770 | MICROPROCESSOR INSTRUCTION COMPLETION COUNTER | Apr 17, 1989 | Abandoned |
Array
(
[id] => 2769090
[patent_doc_number] => 05060139
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-22
[patent_title] => 'Futurebus interrupt subsystem apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/335027
[patent_app_country] => US
[patent_app_date] => 1989-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/060/05060139.pdf
[firstpage_image] =>[orig_patent_app_number] => 335027
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/335027 | Futurebus interrupt subsystem apparatus | Apr 6, 1989 | Issued |
Array
(
[id] => 2907601
[patent_doc_number] => 05241633
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-31
[patent_title] => 'Instruction handling sequence control system for simultaneous execution of instructions'
[patent_app_type] => 1
[patent_app_number] => 7/331970
[patent_app_country] => US
[patent_app_date] => 1989-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 17
[patent_no_of_words] => 5970
[patent_no_of_claims] => 1
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[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/241/05241633.pdf
[firstpage_image] =>[orig_patent_app_number] => 331970
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/331970 | Instruction handling sequence control system for simultaneous execution of instructions | Apr 2, 1989 | Issued |
| 07/327475 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A MICROPROGRAM | Mar 21, 1989 | Abandoned |
Array
(
[id] => 2843280
[patent_doc_number] => 05175850
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-29
[patent_title] => 'Processing system for storing related information without modifying selected basic data or stored relational data if previous storage detected'
[patent_app_type] => 1
[patent_app_number] => 7/323288
[patent_app_country] => US
[patent_app_date] => 1989-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 2685
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/175/05175850.pdf
[firstpage_image] =>[orig_patent_app_number] => 323288
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/323288 | Processing system for storing related information without modifying selected basic data or stored relational data if previous storage detected | Mar 13, 1989 | Issued |
Array
(
[id] => 2795506
[patent_doc_number] => 05165030
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-17
[patent_title] => 'Method and system for dynamic creation of data stream based upon system parameters and operator selections'
[patent_app_type] => 1
[patent_app_number] => 7/321931
[patent_app_country] => US
[patent_app_date] => 1989-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/05/165/05165030.pdf
[firstpage_image] =>[orig_patent_app_number] => 321931
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/321931 | Method and system for dynamic creation of data stream based upon system parameters and operator selections | Mar 9, 1989 | Issued |
Array
(
[id] => 2818430
[patent_doc_number] => 05148543
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-15
[patent_title] => 'IC card with a stored data change inhibition function'
[patent_app_type] => 1
[patent_app_number] => 7/321641
[patent_app_country] => US
[patent_app_date] => 1989-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 3083
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/148/05148543.pdf
[firstpage_image] =>[orig_patent_app_number] => 321641
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/321641 | IC card with a stored data change inhibition function | Mar 8, 1989 | Issued |
| 07/318815 | PROCESSING SYSTEM HAVING A STORAGE SET WITH DATA DESIGNATING OPERATION STATE FROM OPERATION STATES IN INSTRUCTION MEMORY SET WITH APPLICATION SPECIFIC BLOCK | Mar 2, 1989 | Abandoned |
Array
(
[id] => 2821913
[patent_doc_number] => 05086504
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-02-04
[patent_title] => 'Method for performing computer system functions defined by a hierarchial programming language having default nodes'
[patent_app_type] => 1
[patent_app_number] => 7/316759
[patent_app_country] => US
[patent_app_date] => 1989-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/086/05086504.pdf
[firstpage_image] =>[orig_patent_app_number] => 316759
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/316759 | Method for performing computer system functions defined by a hierarchial programming language having default nodes | Feb 27, 1989 | Issued |
Array
(
[id] => 2892415
[patent_doc_number] => 05109488
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-28
[patent_title] => 'Data processing system buffering sequential data for cyclically recurrent delay times, memory address generator for use in such system'
[patent_app_type] => 1
[patent_app_number] => 7/316720
[patent_app_country] => US
[patent_app_date] => 1989-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/109/05109488.pdf
[firstpage_image] =>[orig_patent_app_number] => 316720
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/316720 | Data processing system buffering sequential data for cyclically recurrent delay times, memory address generator for use in such system | Feb 27, 1989 | Issued |
Array
(
[id] => 2789925
[patent_doc_number] => 05088025
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-02-11
[patent_title] => 'Input/output processor control system with a plurality of staging buffers and data buffers'
[patent_app_type] => 1
[patent_app_number] => 7/313116
[patent_app_country] => US
[patent_app_date] => 1989-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => patents/05/088/05088025.pdf
[firstpage_image] =>[orig_patent_app_number] => 313116
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/313116 | Input/output processor control system with a plurality of staging buffers and data buffers | Feb 20, 1989 | Issued |
Array
(
[id] => 2688575
[patent_doc_number] => 05067069
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-11-19
[patent_title] => 'Control of multiple functional units with parallel operation in a microcoded execution unit'
[patent_app_type] => 1
[patent_app_number] => 7/306832
[patent_app_country] => US
[patent_app_date] => 1989-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[pdf_file] => patents/05/067/05067069.pdf
[firstpage_image] =>[orig_patent_app_number] => 306832
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/306832 | Control of multiple functional units with parallel operation in a microcoded execution unit | Feb 2, 1989 | Issued |
| 07/299426 | CHARACTER PROCESSING DEVICE ADAPTED TO PERFORM DOCUMENT-EDITING PROCESSING AND TYPEWRITING PROCESSING | Jan 22, 1989 | Abandoned |