Search

Daniel H. Pan

Examiner (ID: 18277)

Most Active Art Unit
2182
Art Unit(s)
2302, 2182, 2183, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1279
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16045979 [patent_doc_number] => 10684861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Enhanced performance-aware instruction scheduling [patent_app_type] => utility [patent_app_number] => 15/714091 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4604 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714091 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/714091
Enhanced performance-aware instruction scheduling Sep 24, 2017 Issued
Array ( [id] => 14076599 [patent_doc_number] => 20190087187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => PREDICTING A TABLE OF CONTENTS POINTER VALUE RESPONSIVE TO BRANCHING TO A SUBROUTINE [patent_app_type] => utility [patent_app_number] => 15/708223 [patent_app_country] => US [patent_app_date] => 2017-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15708223 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/708223
Predicting a table of contents pointer value responsive to branching to a subroutine Sep 18, 2017 Issued
Array ( [id] => 14856557 [patent_doc_number] => 10417005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Multi-multidimensional computer architecture for big data applications [patent_app_type] => utility [patent_app_number] => 15/700488 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8432 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15700488 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/700488
Multi-multidimensional computer architecture for big data applications Sep 10, 2017 Issued
Array ( [id] => 14735523 [patent_doc_number] => 10387161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Techniques for capturing state information and performing actions for threads in a multi-threaded computing environment [patent_app_type] => utility [patent_app_number] => 15/694673 [patent_app_country] => US [patent_app_date] => 2017-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 14397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694673 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/694673
Techniques for capturing state information and performing actions for threads in a multi-threaded computing environment Aug 31, 2017 Issued
Array ( [id] => 14489319 [patent_doc_number] => 10331447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Providing efficient recursion handling using compressed return address stacks (CRASs) in processor-based systems [patent_app_type] => utility [patent_app_number] => 15/690812 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6276 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690812 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690812
Providing efficient recursion handling using compressed return address stacks (CRASs) in processor-based systems Aug 29, 2017 Issued
Array ( [id] => 13706771 [patent_doc_number] => 20170364340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => Systems and Methods for Using Error Correction and Pipelining Techniques for an Access Triggered Computer Architecture [patent_app_type] => utility [patent_app_number] => 15/688063 [patent_app_country] => US [patent_app_date] => 2017-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15688063 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/688063
Systems and methods for using error correction and pipelining techniques for an access triggered computer architecture Aug 27, 2017 Issued
Array ( [id] => 12221711 [patent_doc_number] => 20180060071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'ASSOCIATING WORKING SETS AND THREADS' [patent_app_type] => utility [patent_app_number] => 15/687173 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 41335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687173 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687173
Associating working sets and threads Aug 24, 2017 Issued
Array ( [id] => 12140094 [patent_doc_number] => 20180018177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'METHOD AND APPARATUS FOR SPECULATIVE VECTORIZATION' [patent_app_type] => utility [patent_app_number] => 15/653403 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15390 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15653403 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/653403
METHOD AND APPARATUS FOR SPECULATIVE VECTORIZATION Jul 17, 2017 Abandoned
Array ( [id] => 13830383 [patent_doc_number] => 20190018676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => MANAGING BACKEND RESOURCES VIA FRONTEND STEERING OR STALLS [patent_app_type] => utility [patent_app_number] => 15/651558 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651558 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651558
Managing backend resources via frontend steering or stalls Jul 16, 2017 Issued
Array ( [id] => 12234880 [patent_doc_number] => 20180067743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR SETTING AN OUTPUT MASK IN A DESTINATION WRITEMASK REGISTER FROM A SOURCE WRITE MASK REGISTER USING AN INPUT WRITEMASK AND IMMEDIATE' [patent_app_type] => utility [patent_app_number] => 15/647123 [patent_app_country] => US [patent_app_date] => 2017-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 21357 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15647123 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/647123
Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate Jul 10, 2017 Issued
Array ( [id] => 13919671 [patent_doc_number] => 10203958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Streaming engine with stream metadata saving for context switching [patent_app_type] => utility [patent_app_number] => 15/635409 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 40 [patent_no_of_words] => 22759 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 428 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15635409 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/635409
Streaming engine with stream metadata saving for context switching Jun 27, 2017 Issued
Array ( [id] => 14719701 [patent_doc_number] => 20190250914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => VECTOR REGISTER ACCESS [patent_app_type] => utility [patent_app_number] => 16/314882 [patent_app_country] => US [patent_app_date] => 2017-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16314882 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/314882
Vector register access Jun 14, 2017 Issued
Array ( [id] => 12120929 [patent_doc_number] => 20180004515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'PROCESSOR AND CONTROL METHOD OF PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/606050 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5763 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15606050 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/606050
Processor and control method of processor for address generating and address displacement May 25, 2017 Issued
Array ( [id] => 12331635 [patent_doc_number] => 09946539 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-17 [patent_title] => Accessing data in multi-dimensional tensors using adders [patent_app_type] => utility [patent_app_number] => 15/603061 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603061 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/603061
Accessing data in multi-dimensional tensors using adders May 22, 2017 Issued
Array ( [id] => 11838634 [patent_doc_number] => 20170220353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'STACK POINTER VALUE PREDICTION' [patent_app_type] => utility [patent_app_number] => 15/489975 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10024 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15489975 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/489975
STACK POINTER VALUE PREDICTION Apr 17, 2017 Abandoned
Array ( [id] => 14330649 [patent_doc_number] => 10296343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Hybrid atomicity support for a binary translation based microprocessor [patent_app_type] => utility [patent_app_number] => 15/474666 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 15331 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15474666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/474666
Hybrid atomicity support for a binary translation based microprocessor Mar 29, 2017 Issued
Array ( [id] => 13467143 [patent_doc_number] => 20180285114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => Method and Apparatus for Augmentation and Disambiguation of Branch History In Pipelined Branch Predictors [patent_app_type] => utility [patent_app_number] => 15/471001 [patent_app_country] => US [patent_app_date] => 2017-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15471001 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/471001
Method and apparatus for augmentation and disambiguation of branch history in pipelined branch predictors Mar 27, 2017 Issued
Array ( [id] => 14395157 [patent_doc_number] => 10310862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Data processing [patent_app_type] => utility [patent_app_number] => 15/464727 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5011 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15464727 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/464727
Data processing Mar 20, 2017 Issued
Array ( [id] => 11716902 [patent_doc_number] => 20170185401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'DATA READ/WRITE METHOD AND APPARATUS, STORAGE DEVICE, AND COMPUTER SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/462057 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15462057 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/462057
Data read/write method and apparatus, storage device, and computer system Mar 16, 2017 Issued
Array ( [id] => 14330665 [patent_doc_number] => 10296351 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-21 [patent_title] => Computer vision processing in hardware data paths [patent_app_type] => utility [patent_app_number] => 15/459284 [patent_app_country] => US [patent_app_date] => 2017-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9855 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15459284 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/459284
Computer vision processing in hardware data paths Mar 14, 2017 Issued
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