Search

Daniel H. Pan

Examiner (ID: 18277)

Most Active Art Unit
2182
Art Unit(s)
2302, 2182, 2183, 2783, 2315, 2899
Total Applications
1471
Issued Applications
1279
Pending Applications
50
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11838625 [patent_doc_number] => 20170220345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'ACCESSING DATA IN MULTI-DIMENSIONAL TENSORS' [patent_app_type] => utility [patent_app_number] => 15/456812 [patent_app_country] => US [patent_app_date] => 2017-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9331 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15456812 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/456812
Accessing data in multi-dimensional tensors Mar 12, 2017 Issued
Array ( [id] => 11708872 [patent_doc_number] => 20170177371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Method and Apparatus for Detecting Memory Conflicts Using Distinguished Memory Addresses' [patent_app_type] => utility [patent_app_number] => 15/455070 [patent_app_country] => US [patent_app_date] => 2017-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15455070 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/455070
Method and apparatus for detecting memory conflicts using distinguished memory addresses Mar 8, 2017 Issued
Array ( [id] => 13417355 [patent_doc_number] => 20180260220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => VECTOR PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 15/454214 [patent_app_country] => US [patent_app_date] => 2017-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15454214 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/454214
Vector processing unit Mar 8, 2017 Issued
Array ( [id] => 13417367 [patent_doc_number] => 20180260226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => SPIN LOOP DELAY INSTRUCTION [patent_app_type] => utility [patent_app_number] => 15/453265 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453265 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/453265
Spin loop delay instruction Mar 7, 2017 Issued
Array ( [id] => 13417351 [patent_doc_number] => 20180260218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => INSTRUCTION SET ARCHITECTURES FOR FINE-GRAINED HETEROGENEOUS PROCESSING [patent_app_type] => utility [patent_app_number] => 15/452150 [patent_app_country] => US [patent_app_date] => 2017-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452150 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452150
INSTRUCTION SET ARCHITECTURES FOR FINE-GRAINED HETEROGENEOUS PROCESSING Mar 6, 2017 Abandoned
Array ( [id] => 14364357 [patent_doc_number] => 10303482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Dynamic processor frequency selection [patent_app_type] => utility [patent_app_number] => 15/451846 [patent_app_country] => US [patent_app_date] => 2017-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15451846 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/451846
Dynamic processor frequency selection Mar 6, 2017 Issued
Array ( [id] => 13767607 [patent_doc_number] => 10176147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods [patent_app_type] => utility [patent_app_number] => 15/452299 [patent_app_country] => US [patent_app_date] => 2017-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17283 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452299 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452299
Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods Mar 6, 2017 Issued
Array ( [id] => 13403513 [patent_doc_number] => 20180253299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => DEFER BUFFER [patent_app_type] => utility [patent_app_number] => 15/450430 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450430 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450430
Defer buffer Mar 5, 2017 Issued
Array ( [id] => 11709017 [patent_doc_number] => 20170177517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'RECONFIGURABLE INTERCONNECTED PROGRAMMABLE PROCESSORS' [patent_app_type] => utility [patent_app_number] => 15/449852 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6940 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15449852 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/449852
Reconfigurable interconnected programmable processors Mar 2, 2017 Issued
Array ( [id] => 14149375 [patent_doc_number] => 10255068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Dynamically selecting a memory boundary to be used in performing operations [patent_app_type] => utility [patent_app_number] => 15/449269 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 33 [patent_no_of_words] => 21131 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15449269 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/449269
Dynamically selecting a memory boundary to be used in performing operations Mar 2, 2017 Issued
Array ( [id] => 11938544 [patent_doc_number] => 20170242694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A DOUBLE BLOCKED SUM OF ABSOLUTE DIFFERENCES' [patent_app_type] => utility [patent_app_number] => 15/445741 [patent_app_country] => US [patent_app_date] => 2017-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 16880 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15445741 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/445741
Systems, apparatuses, and methods for performing a double blocked sum of absolute differences Feb 27, 2017 Issued
Array ( [id] => 13291745 [patent_doc_number] => 10157064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Processing of multiple instruction streams in a parallel slice processor [patent_app_type] => utility [patent_app_number] => 15/442810 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5051 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15442810 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/442810
Processing of multiple instruction streams in a parallel slice processor Feb 26, 2017 Issued
Array ( [id] => 14035029 [patent_doc_number] => 10229266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Architected store and verify guard word instructions [patent_app_type] => utility [patent_app_number] => 15/435474 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 11608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15435474 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/435474
Architected store and verify guard word instructions Feb 16, 2017 Issued
Array ( [id] => 11672222 [patent_doc_number] => 20170160944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'INTEGRATING SIGN EXTENSIONS FOR LOADS' [patent_app_type] => utility [patent_app_number] => 15/436138 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15436138 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/436138
Integrating sign extensions for loads Feb 16, 2017 Issued
Array ( [id] => 11665171 [patent_doc_number] => 20170153890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'HIGHLY INTEGRATED SCALABLE, FLEXIBLE DSP MEGAMODULE ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 15/429205 [patent_app_country] => US [patent_app_date] => 2017-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 17100 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15429205 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/429205
Highly integrated scalable, flexible DSP megamodule architecture Feb 9, 2017 Issued
Array ( [id] => 14091779 [patent_doc_number] => 10241794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Apparatus and methods to support counted loop exits in a multi-strand loop processor [patent_app_type] => utility [patent_app_number] => 15/391703 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 36 [patent_no_of_words] => 23725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15391703 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/391703
Apparatus and methods to support counted loop exits in a multi-strand loop processor Dec 26, 2016 Issued
Array ( [id] => 12868663 [patent_doc_number] => 20180181396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => METHOD TO DO CONTROL SPECULATION ON LOADS IN A HIGH PERFORMANCE STRAND-BASED LOOP ACCELERATOR [patent_app_type] => utility [patent_app_number] => 15/391789 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15391789 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/391789
Method to do control speculation on loads in a high performance strand-based loop accelerator Dec 26, 2016 Issued
Array ( [id] => 12868681 [patent_doc_number] => 20180181402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => PROCESSOR PREFETCH THROTTLING BASED ON SHORT STREAMS [patent_app_type] => utility [patent_app_number] => 15/390588 [patent_app_country] => US [patent_app_date] => 2016-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15390588 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/390588
Processor prefetch throttling based on short streams Dec 25, 2016 Issued
Array ( [id] => 14091793 [patent_doc_number] => 10241801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator [patent_app_type] => utility [patent_app_number] => 15/390194 [patent_app_country] => US [patent_app_date] => 2016-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 17821 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15390194 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/390194
Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator Dec 22, 2016 Issued
Array ( [id] => 15248253 [patent_doc_number] => 10509651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Montgomery multiplication processors, methods, systems, and instructions [patent_app_type] => utility [patent_app_number] => 15/388642 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 16171 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15388642 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/388642
Montgomery multiplication processors, methods, systems, and instructions Dec 21, 2016 Issued
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