Daniel J. Rohrhoff

Array ( [id] => 8743047 [patent_doc_number] => 20130082764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'APPARATUS AND METHOD TO COMBINE PIN FUNCTIONALITY IN AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/250677 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13250677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7720641 [patent_doc_number] => 20120009976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'RECESS GATE TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/242724 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5840 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20120009976.pdf [firstpage_image] =>[orig_patent_app_number] => 13242724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7716946 [patent_doc_number] => 20120007075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'SEMICONDUCTOR CHIP WITH BACKSIDE CONDUCTOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/239872 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5506 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20120007075.pdf [firstpage_image] =>[orig_patent_app_number] => 13239872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7783179 [patent_doc_number] => 20120044735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'STRUCTURES WITH INCREASED PHOTO-ALIGNMENT MARGINS' [patent_app_type] => utility [patent_app_number] => 13/233609 [patent_app_country] => US [patent_app_date] => 2011-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 10795 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20120044735.pdf [firstpage_image] =>[orig_patent_app_number] => 13233609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7711211 [patent_doc_number] => 20120003792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'STACKED DIE PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/231953 [patent_app_country] => US [patent_app_date] => 2011-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2998 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13231953 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7656934 [patent_doc_number] => 20110306203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'INTERCONNECT STRUCTURE AND METHOD OF MANUFACTURING A DAMASCENE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/218035 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0306/20110306203.pdf [firstpage_image] =>[orig_patent_app_number] => 13218035 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7558944 [patent_doc_number] => 20110272775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => '3D INTEGRATED CIRCUIT SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/183373 [patent_app_country] => US [patent_app_date] => 2011-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2458 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20110272775.pdf [firstpage_image] =>[orig_patent_app_number] => 13183373 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8071931 [patent_doc_number] => 20110241057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'HIGH-EFFICIENCY LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/161835 [patent_app_country] => US [patent_app_date] => 2011-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2107 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241057.pdf [firstpage_image] =>[orig_patent_app_number] => 13161835 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7488956 [patent_doc_number] => 20110237008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'OPTOELECTRONIC SUBSTRATE AND METHODS OF MAKING SAME' [patent_app_type] => utility [patent_app_number] => 13/154510 [patent_app_country] => US [patent_app_date] => 2011-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5492 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20110237008.pdf [firstpage_image] =>[orig_patent_app_number] => 13154510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7480537 [patent_doc_number] => 20110233547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/153078 [patent_app_country] => US [patent_app_date] => 2011-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8292 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20110233547.pdf [firstpage_image] =>[orig_patent_app_number] => 13153078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7572217 [patent_doc_number] => 20110267873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'NON-VOLATILE MEMORY WITH PROGRAMMABLE CAPACITANCE' [patent_app_type] => utility [patent_app_number] => 13/151440 [patent_app_country] => US [patent_app_date] => 2011-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20110267873.pdf [firstpage_image] =>[orig_patent_app_number] => 13151440 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8578244 [patent_doc_number] => 08344455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Semiconductor device and fabrication method for the same' [patent_app_type] => utility [patent_app_number] => 13/149554 [patent_app_country] => US [patent_app_date] => 2011-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 5797 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13149554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6010496 [patent_doc_number] => 20110220893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'Array Substrate for Liquid Crystal Display Device and Method of Fabricating the Same' [patent_app_type] => utility [patent_app_number] => 13/113922 [patent_app_country] => US [patent_app_date] => 2011-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4335 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20110220893.pdf [firstpage_image] =>[orig_patent_app_number] => 13113922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8872156 [patent_doc_number] => 08467539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'High transmission loss cushion' [patent_app_type] => utility [patent_app_number] => 13/078258 [patent_app_country] => US [patent_app_date] => 2011-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 5500 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13078258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6189091 [patent_doc_number] => 20110171796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'VERTICAL WRAP-AROUND-GATE FIELD-EFFECT-TRANSISTOR FOR HIGH DENSITY, LOW VOLTAGE LOGIC AND MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 13/071628 [patent_app_country] => US [patent_app_date] => 2011-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 12016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20110171796.pdf [firstpage_image] =>[orig_patent_app_number] => 13071628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6098922 [patent_doc_number] => 20110163407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'PHOTOELECTRIC CONVERSION DEVICE, METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE, AND IMAGE PICKUP SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/049101 [patent_app_country] => US [patent_app_date] => 2011-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9209 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20110163407.pdf [firstpage_image] =>[orig_patent_app_number] => 13049101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6075387 [patent_doc_number] => 20110140277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/030861 [patent_app_country] => US [patent_app_date] => 2011-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7261 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20110140277.pdf [firstpage_image] =>[orig_patent_app_number] => 13030861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9824021 [patent_doc_number] => 08933509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-13 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 13/023427 [patent_app_country] => US [patent_app_date] => 2011-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 4262 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13023427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5940751 [patent_doc_number] => 20110101371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'Gallium nitride semiconductor' [patent_app_type] => utility [patent_app_number] => 12/930179 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7550 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20110101371.pdf [firstpage_image] =>[orig_patent_app_number] => 12930179 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6375875 [patent_doc_number] => 20100301449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'METHODS AND APPARATUS FOR FORMING LINE AND PILLAR STRUCTURES FOR THREE DIMENSIONAL MEMORY ARRAYS USING A DOUBLE SUBTRACTIVE PROCESS AND IMPRINT LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 12/856392 [patent_app_country] => US [patent_app_date] => 2010-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8824 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20100301449.pdf [firstpage_image] =>[orig_patent_app_number] => 12856392 [rel_patent_id] =>[rel_patent_doc_number] =>)