
Daniel J. Rohrhoff
Examiner (ID: 7103, Phone: (571)270-7624 , Office: P/3637 )
| Most Active Art Unit | 3637 |
| Art Unit(s) | 3637 |
| Total Applications | 1573 |
| Issued Applications | 1199 |
| Pending Applications | 98 |
| Abandoned Applications | 307 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5145700
[patent_doc_number] => 20070045754
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-01
[patent_title] => 'Semiconductor device with recessed L-shaped spacer and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/215103
[patent_app_country] => US
[patent_app_date] => 2005-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2425
[patent_no_of_claims] => 20
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0045/20070045754.pdf
[firstpage_image] =>[orig_patent_app_number] => 11215103
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/215103 | Semiconductor device with recessed L-shaped spacer and method of fabricating the same | Aug 29, 2005 | Issued |
Array
(
[id] => 5736158
[patent_doc_number] => 20060006548
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-12
[patent_title] => 'H2 plasma treatment'
[patent_app_type] => utility
[patent_app_number] => 11/215367
[patent_app_country] => US
[patent_app_date] => 2005-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[patent_no_of_words] => 7516
[patent_no_of_claims] => 49
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[pdf_file] => publications/A1/0006/20060006548.pdf
[firstpage_image] =>[orig_patent_app_number] => 11215367
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/215367 | Electronic apparatus having a core conductive structure within an insulating layer | Aug 28, 2005 | Issued |
Array
(
[id] => 5796462
[patent_doc_number] => 20060033139
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-16
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/204163
[patent_app_country] => US
[patent_app_date] => 2005-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => publications/A1/0033/20060033139.pdf
[firstpage_image] =>[orig_patent_app_number] => 11204163
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/204163 | Semiconductor device and method of manufacturing the same | Aug 15, 2005 | Issued |
Array
(
[id] => 5818035
[patent_doc_number] => 20060022348
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-02
[patent_title] => 'Method of sealing low-k dielectrics and devices made thereby'
[patent_app_type] => utility
[patent_app_number] => 11/204613
[patent_app_country] => US
[patent_app_date] => 2005-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4506
[patent_no_of_claims] => 10
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[pdf_file] => publications/A1/0022/20060022348.pdf
[firstpage_image] =>[orig_patent_app_number] => 11204613
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/204613 | Method of sealing low-k dielectrics and devices made thereby | Aug 14, 2005 | Abandoned |
Array
(
[id] => 383322
[patent_doc_number] => 07307274
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-12-11
[patent_title] => 'Transistors having reinforcement layer patterns and methods of forming the same'
[patent_app_type] => utility
[patent_app_number] => 11/204564
[patent_app_country] => US
[patent_app_date] => 2005-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
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[patent_no_of_words] => 6606
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[pdf_file] => patents/07/307/07307274.pdf
[firstpage_image] =>[orig_patent_app_number] => 11204564
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/204564 | Transistors having reinforcement layer patterns and methods of forming the same | Aug 14, 2005 | Issued |
Array
(
[id] => 5708092
[patent_doc_number] => 20060049436
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-09
[patent_title] => 'Semiconductor component with a MOS transistor'
[patent_app_type] => utility
[patent_app_number] => 11/202634
[patent_app_country] => US
[patent_app_date] => 2005-08-12
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[firstpage_image] =>[orig_patent_app_number] => 11202634
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/202634 | Semiconductor component with a MOS transistor | Aug 11, 2005 | Issued |
Array
(
[id] => 5790842
[patent_doc_number] => 20060011947
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-19
[patent_title] => 'Semiconductor structures and memory device constructions'
[patent_app_type] => utility
[patent_app_number] => 11/201824
[patent_app_country] => US
[patent_app_date] => 2005-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 129
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[patent_no_of_words] => 14122
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[pdf_file] => publications/A1/0011/20060011947.pdf
[firstpage_image] =>[orig_patent_app_number] => 11201824
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/201824 | Semiconductor structures and memory device constructions | Aug 9, 2005 | Issued |
Array
(
[id] => 7229086
[patent_doc_number] => 20050269718
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-08
[patent_title] => 'Optimized driver layout for integrated circuits with staggered bond pads'
[patent_app_type] => utility
[patent_app_number] => 11/200903
[patent_app_country] => US
[patent_app_date] => 2005-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 1762
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0269/20050269718.pdf
[firstpage_image] =>[orig_patent_app_number] => 11200903
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/200903 | Optimized driver layout for integrated circuits with staggered bond pads | Aug 8, 2005 | Abandoned |
Array
(
[id] => 5670318
[patent_doc_number] => 20060175672
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-10
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/197593
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[firstpage_image] =>[orig_patent_app_number] => 11197593
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/197593 | Semiconductor device and method of manufacturing the same | Aug 4, 2005 | Issued |
Array
(
[id] => 539632
[patent_doc_number] => 07176519
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-13
[patent_title] => 'Memory cell, memory cell arrangement and method for the production of a memory cell'
[patent_app_type] => utility
[patent_app_number] => 11/197803
[patent_app_country] => US
[patent_app_date] => 2005-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 7424
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[pdf_file] => patents/07/176/07176519.pdf
[firstpage_image] =>[orig_patent_app_number] => 11197803
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/197803 | Memory cell, memory cell arrangement and method for the production of a memory cell | Aug 4, 2005 | Issued |
Array
(
[id] => 587253
[patent_doc_number] => 07446369
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-11-04
[patent_title] => 'SONOS memory cell having high-K dielectric'
[patent_app_type] => utility
[patent_app_number] => 11/196434
[patent_app_country] => US
[patent_app_date] => 2005-08-04
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[pdf_file] => patents/07/446/07446369.pdf
[firstpage_image] =>[orig_patent_app_number] => 11196434
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/196434 | SONOS memory cell having high-K dielectric | Aug 3, 2005 | Issued |
Array
(
[id] => 5049045
[patent_doc_number] => 20070029589
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-08
[patent_title] => 'Reduced crosstalk CMOS image sensors'
[patent_app_type] => utility
[patent_app_number] => 11/197004
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[firstpage_image] =>[orig_patent_app_number] => 11197004
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/197004 | Reduced crosstalk CMOS image sensors | Aug 3, 2005 | Issued |
Array
(
[id] => 5724242
[patent_doc_number] => 20060055002
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-16
[patent_title] => 'Methods for enhancing die saw and packaging reliability'
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[patent_app_number] => 11/196184
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[firstpage_image] =>[orig_patent_app_number] => 11196184
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/196184 | Methods for enhancing die saw and packaging reliability | Aug 2, 2005 | Abandoned |
Array
(
[id] => 5709213
[patent_doc_number] => 20060050558
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-09
[patent_title] => 'Semiconductor device and an integrated curcuit card'
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[pdf_file] => publications/A1/0050/20060050558.pdf
[firstpage_image] =>[orig_patent_app_number] => 11195683
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/195683 | Semiconductor device and an integrated circuit card | Aug 2, 2005 | Issued |
Array
(
[id] => 7213839
[patent_doc_number] => 20050253162
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[patent_title] => 'LIGHT EMITTING DIODE HAVING A P-N JUNCTION DOPED WITH ONE OR MORE LUMINESCENT ACTIVATOR IONS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/161403 | LIGHT EMITTING DIODE HAVING A P-N JUNCTION DOPED WITH ONE OR MORE LUMINESCENT ACTIVATOR IONS | Aug 1, 2005 | Abandoned |
Array
(
[id] => 5138965
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[patent_title] => 'LIGHT EMITTING DIODE AND METHOD FOR IMPROVING LUMINESCENCE EFFICIENCY THEREOF'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/161363 | LIGHT EMITTING DIODE AND METHOD FOR IMPROVING LUMINESCENCE EFFICIENCY THEREOF | Jul 31, 2005 | Abandoned |
Array
(
[id] => 5239716
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[patent_title] => 'Split gate storage device including a horizontal first gate and a vertical second gate in a trench'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/188603 | Split gate storage device including a horizontal first gate and a vertical second gate in a trench | Jul 24, 2005 | Issued |
Array
(
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[patent_title] => 'Flat panel display device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/187873 | Flat panel display device | Jul 24, 2005 | Issued |
Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/179404 | Bipolar transistor and fabrication method of the same | Jul 11, 2005 | Issued |