Search

Daniel J. Wiley

Examiner (ID: 7827, Phone: (571)270-7324 , Office: P/3679 )

Most Active Art Unit
3678
Art Unit(s)
3678, 3679
Total Applications
1207
Issued Applications
906
Pending Applications
65
Abandoned Applications
257

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20222754 [patent_doc_number] => 20250285685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => MEMORY SYSTEMS, OPERATING METHODS, AND READABLE STORAGE MEDIUMS [patent_app_type] => utility [patent_app_number] => 18/743818 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743818 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743818
MEMORY SYSTEMS, OPERATING METHODS, AND READABLE STORAGE MEDIUMS Jun 13, 2024 Issued
Array ( [id] => 19618924 [patent_doc_number] => 20240404604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => DETERMINING OFFSETS FOR MEMORY READ OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/733187 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733187 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733187
Determining offsets for memory read operations Jun 3, 2024 Issued
Array ( [id] => 20124254 [patent_doc_number] => 20250239285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => DEVICE HAVING ROWS OF MRAM CELLS CONFIGURED FOR CONCURRENT WRITING AND READING [patent_app_type] => utility [patent_app_number] => 18/733241 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2389 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733241 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733241
Device having rows of MRAM cells configured for concurrent writing and reading Jun 3, 2024 Issued
Array ( [id] => 19618930 [patent_doc_number] => 20240404610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => READ OPERATIONS WITH OFFSET FOR SLOW CHARGE LOSS [patent_app_type] => utility [patent_app_number] => 18/679956 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679956 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/679956
Read operations with offset for slow charge loss May 30, 2024 Issued
Array ( [id] => 20161132 [patent_doc_number] => 12387765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Memory modules including a mirroring circuit and methods of operating the same [patent_app_type] => utility [patent_app_number] => 18/670778 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 7896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670778 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670778
Memory modules including a mirroring circuit and methods of operating the same May 21, 2024 Issued
Array ( [id] => 20215122 [patent_doc_number] => 12411775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Dual address encoding for logical-to-physical mapping [patent_app_type] => utility [patent_app_number] => 18/662743 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6079 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662743 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662743
Dual address encoding for logical-to-physical mapping May 12, 2024 Issued
Array ( [id] => 19986764 [patent_doc_number] => 20250124986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => SENSING APPARATUS FOR NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/656630 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18656630 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/656630
Sensing apparatus for non-volatile memory May 6, 2024 Issued
Array ( [id] => 20324365 [patent_doc_number] => 20250336453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => PERFORMANCE SAVING DURING BLOCK JUMPING [patent_app_type] => utility [patent_app_number] => 18/647612 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647612 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647612
PERFORMANCE SAVING DURING BLOCK JUMPING Apr 25, 2024 Pending
Array ( [id] => 19900046 [patent_doc_number] => 12277978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Selective and dynamic deployment of error correction code techniques in integrated circuit memory devices [patent_app_type] => utility [patent_app_number] => 18/636901 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 17901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636901 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/636901
Selective and dynamic deployment of error correction code techniques in integrated circuit memory devices Apr 15, 2024 Issued
Array ( [id] => 20530180 [patent_doc_number] => 12548621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Socket design for a memory device [patent_app_type] => utility [patent_app_number] => 18/616989 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7307 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18616989 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/616989
Socket design for a memory device Mar 25, 2024 Issued
Array ( [id] => 20537554 [patent_doc_number] => 12554631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Information processing apparatus and memory system [patent_app_type] => utility [patent_app_number] => 18/601791 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 35 [patent_no_of_words] => 7274 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601791 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/601791
Information processing apparatus and memory system Mar 10, 2024 Issued
Array ( [id] => 19269058 [patent_doc_number] => 20240212762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => SEMICONDUCTOR MEMORY DEVICES WITH DIELECTRIC FIN STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/598793 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18598793 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/598793
SEMICONDUCTOR MEMORY DEVICES WITH DIELECTRIC FIN STRUCTURES Mar 6, 2024 Pending
Array ( [id] => 20389115 [patent_doc_number] => 12488848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Read parameter zoning [patent_app_type] => utility [patent_app_number] => 18/598656 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 11023 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18598656 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/598656
Read parameter zoning Mar 6, 2024 Issued
Array ( [id] => 19269053 [patent_doc_number] => 20240212757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => NONVOLATILE SEMICONDUCTOR MEMORY INCLUDING A READ OPERATION [patent_app_type] => utility [patent_app_number] => 18/596753 [patent_app_country] => US [patent_app_date] => 2024-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596753 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596753
Nonvolatile semiconductor memory including a read operation Mar 5, 2024 Issued
Array ( [id] => 19392520 [patent_doc_number] => 20240282390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => SLOW-CHARGE-LOSS TRACKING USING FEEDBACK-CONTROL LOOP [patent_app_type] => utility [patent_app_number] => 18/583197 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583197 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/583197
Slow-charge-loss tracking using feedback-control loop Feb 20, 2024 Issued
Array ( [id] => 19221237 [patent_doc_number] => 20240185941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => METHODS FOR RECOVERY FOR MEMORY SYSTEMS AND MEMORY SYSTEMS EMPLOYING THE SAME [patent_app_type] => utility [patent_app_number] => 18/444176 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444176 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444176
Methods for recovery for memory systems and memory systems employing the same Feb 15, 2024 Issued
Array ( [id] => 20469242 [patent_doc_number] => 12525284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Column select topology supporting increased throughput for writes to memory [patent_app_type] => utility [patent_app_number] => 18/436293 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 3708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436293 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436293
Column select topology supporting increased throughput for writes to memory Feb 7, 2024 Issued
Array ( [id] => 20153162 [patent_doc_number] => 20250253000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/435030 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435030 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435030
Three-dimensional memory device Feb 6, 2024 Issued
Array ( [id] => 20118210 [patent_doc_number] => 12367925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Static random access memory layout [patent_app_type] => utility [patent_app_number] => 18/418779 [patent_app_country] => US [patent_app_date] => 2024-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418779 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/418779
Static random access memory layout Jan 21, 2024 Issued
Array ( [id] => 20258831 [patent_doc_number] => 12431194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Resistive random access memory unit with one-way conduction characteristic and fabricating method thereof [patent_app_type] => utility [patent_app_number] => 18/414880 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 0 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18414880 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/414880
Resistive random access memory unit with one-way conduction characteristic and fabricating method thereof Jan 16, 2024 Issued
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