Search

Daniel J. Wiley

Examiner (ID: 7827, Phone: (571)270-7324 , Office: P/3679 )

Most Active Art Unit
3678
Art Unit(s)
3678, 3679
Total Applications
1207
Issued Applications
906
Pending Applications
65
Abandoned Applications
257

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17787604 [patent_doc_number] => 11410738 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-09 [patent_title] => Word line decoding circuit and memory [patent_app_type] => utility [patent_app_number] => 17/566643 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 7027 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 544 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566643 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566643
Word line decoding circuit and memory Dec 29, 2021 Issued
Array ( [id] => 17536475 [patent_doc_number] => 20220115084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => ADAPTING AN ERROR RECOVERY PROCESS IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/557782 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557782 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/557782
Adapting an error recovery process in a memory sub-system Dec 20, 2021 Issued
Array ( [id] => 17508832 [patent_doc_number] => 20220101935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => METHOD OF TESTING WITH GROUND NOISE [patent_app_type] => utility [patent_app_number] => 17/643188 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643188 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643188
Method of testing with ground noise Dec 7, 2021 Issued
Array ( [id] => 18394584 [patent_doc_number] => 20230162805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/531825 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531825 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531825
Memory device and operation method thereof Nov 21, 2021 Issued
Array ( [id] => 18969382 [patent_doc_number] => 11903194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Integrated circuit [patent_app_type] => utility [patent_app_number] => 17/529027 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3557 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529027 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/529027
Integrated circuit Nov 16, 2021 Issued
Array ( [id] => 18918985 [patent_doc_number] => 11881273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 17/524535 [patent_app_country] => US [patent_app_date] => 2021-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 64 [patent_no_of_words] => 13016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524535 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/524535
Semiconductor storage device Nov 10, 2021 Issued
Array ( [id] => 17566312 [patent_doc_number] => 20220130461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => TIMING PARAMETER ADJUSTMENT MECHANISMS [patent_app_type] => utility [patent_app_number] => 17/518176 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518176 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518176
Timing parameter adjustment mechanisms Nov 2, 2021 Issued
Array ( [id] => 18751300 [patent_doc_number] => 11810618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Extended memory communication [patent_app_type] => utility [patent_app_number] => 17/453136 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 15660 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453136 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453136
Extended memory communication Oct 31, 2021 Issued
Array ( [id] => 19046460 [patent_doc_number] => 11935579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Protection circuit and memory [patent_app_type] => utility [patent_app_number] => 17/451818 [patent_app_country] => US [patent_app_date] => 2021-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5153 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451818 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451818
Protection circuit and memory Oct 20, 2021 Issued
Array ( [id] => 18334474 [patent_doc_number] => 20230126422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => SYSTEMS AND METHODS FOR DYNAMICALLY SENSING A MEMORY BLOCK [patent_app_type] => utility [patent_app_number] => 17/506960 [patent_app_country] => US [patent_app_date] => 2021-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17506960 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/506960
Systems and methods for dynamically sensing a memory block Oct 20, 2021 Issued
Array ( [id] => 19029742 [patent_doc_number] => 11929105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Method of fabricating a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/504005 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5951 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504005 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/504005
Method of fabricating a semiconductor device Oct 17, 2021 Issued
Array ( [id] => 18548040 [patent_doc_number] => 11721398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Techniques for determining memory cell read offsets [patent_app_type] => utility [patent_app_number] => 17/502497 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10844 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502497 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/502497
Techniques for determining memory cell read offsets Oct 14, 2021 Issued
Array ( [id] => 17507571 [patent_doc_number] => 20220100674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => DUAL ADDRESS ENCODING FOR LOGICAL-TO-PHYSICAL MAPPING [patent_app_type] => utility [patent_app_number] => 17/495410 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495410 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495410
Dual address encoding for logical-to-physical mapping Oct 5, 2021 Issued
Array ( [id] => 18008222 [patent_doc_number] => 20220366989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/493438 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17493438 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/493438
Semiconductor memory device and method of operating the same Oct 3, 2021 Issued
Array ( [id] => 17900471 [patent_doc_number] => 20220310133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => SENSE AMPLIFIER, MEMORY AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 17/449658 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9342 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17449658 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/449658
Sense amplifier, memory and control method Sep 29, 2021 Issued
Array ( [id] => 18283236 [patent_doc_number] => 20230098708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => SEMICONDUCTOR MEMORY DEVICES WITH DIELECTRIC FIN STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/490097 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17490097 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/490097
Semiconductor memory devices with dielectric fin structures Sep 29, 2021 Issued
Array ( [id] => 18280285 [patent_doc_number] => 20230095757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => PROGRAMMING TECHNIQUES FOR MEMORY DEVICES HAVING PARTIAL DRAIN-SIDE SELECT GATES [patent_app_type] => utility [patent_app_number] => 17/487634 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487634 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/487634
Programming techniques for memory devices having partial drain-side select gates Sep 27, 2021 Issued
Array ( [id] => 18520634 [patent_doc_number] => 11710528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Data-based polarity write operations [patent_app_type] => utility [patent_app_number] => 17/487792 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 20800 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487792 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/487792
Data-based polarity write operations Sep 27, 2021 Issued
Array ( [id] => 17508822 [patent_doc_number] => 20220101925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => METHOD FOR PROGRAMMING 3D NAND FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 17/486908 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486908 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/486908
Method for programming 3D NAND flash memory Sep 26, 2021 Issued
Array ( [id] => 17402648 [patent_doc_number] => 20220044739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => Iterative Read Calibration Enhanced according to Patterns of Shifts in Read Voltages [patent_app_type] => utility [patent_app_number] => 17/485093 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14855 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485093
Iterative read calibration enhanced according to patterns of shifts in read voltages Sep 23, 2021 Issued
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