Daniel J. Wiley

Array ( [id] => 18743112 [patent_doc_number] => 20230352100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => MEMORY DEVICE AND ASYNCHRONOUS MULTI-PLANE INDEPENDENT READ OPERATION THEREOF [patent_app_type] => utility [patent_app_number] => 18/217987 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18217987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19979999 [patent_doc_number] => 12347485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Establishing bitline, wordline and boost voltages to manage a maximum program voltage level during all levels programming of a memory device [patent_app_type] => utility [patent_app_number] => 18/214080 [patent_app_country] => US [patent_app_date] => 2023-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18214080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19459960 [patent_doc_number] => 12100462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Memory device and multi-pass program operation thereof [patent_app_type] => utility [patent_app_number] => 18/211495 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 11216 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18925517 [patent_doc_number] => 20240028521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => DUAL ADDRESS ENCODING FOR LOGICAL-TO-PHYSICAL MAPPING [patent_app_type] => utility [patent_app_number] => 18/211476 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19444575 [patent_doc_number] => 12094866 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Semiconductor memory system [patent_app_type] => utility [patent_app_number] => 18/203693 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 4719 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203693 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20345801 [patent_doc_number] => 12469536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Memory and electronic device [patent_app_type] => utility [patent_app_number] => 18/323702 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 9426 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18814996 [patent_doc_number] => 20230389334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => MULTI-LEVEL MEMRISTOR ELEMENTS [patent_app_type] => utility [patent_app_number] => 18/323838 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323838 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20305192 [patent_doc_number] => 12451188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Memory programming method, memory device, and memory system [patent_app_type] => utility [patent_app_number] => 18/201685 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201685 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20317969 [patent_doc_number] => 12456524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Memory device, operating method thereof, and verification result generator [patent_app_type] => utility [patent_app_number] => 18/319292 [patent_app_country] => US [patent_app_date] => 2023-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 4719 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18319292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20538560 [patent_doc_number] => 12555639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Memory device including page buffer circuit [patent_app_type] => utility [patent_app_number] => 18/197258 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20538560 [patent_doc_number] => 12555639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Memory device including page buffer circuit [patent_app_type] => utility [patent_app_number] => 18/197258 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20538560 [patent_doc_number] => 12555639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Memory device including page buffer circuit [patent_app_type] => utility [patent_app_number] => 18/197258 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20538560 [patent_doc_number] => 12555639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Memory device including page buffer circuit [patent_app_type] => utility [patent_app_number] => 18/197258 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19670637 [patent_doc_number] => 12183404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Clock signal return scheme for data read in page buffer of memory device [patent_app_type] => utility [patent_app_number] => 18/197526 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 11828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19191165 [patent_doc_number] => 20240170078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => MEMORY DEVICE RELATED TO A VERIFY OPERATION AND METHOD OF OPERATING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/307603 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18307603 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18727603 [patent_doc_number] => 20230341894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => Real-Time Clock Module And Electronic Device [patent_app_type] => utility [patent_app_number] => 18/306552 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18774015 [patent_doc_number] => 20230368845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => PARTIAL BLOCK READ LEVEL VOLTAGE COMPENSATION TO DECREASE READ TRIGGER RATES [patent_app_type] => utility [patent_app_number] => 18/138489 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138489 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19145993 [patent_doc_number] => 20240145008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/304189 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18304189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19205849 [patent_doc_number] => 20240177748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME CAPABLE OF PREVENTING MALFUNCTION DURING READ OPERATION [patent_app_type] => utility [patent_app_number] => 18/304238 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18304238 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18712568 [patent_doc_number] => 20230335201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => CONDITIONAL VALLEY TRACKING DURING CORRECTIVE READS [patent_app_type] => utility [patent_app_number] => 18/135915 [patent_app_country] => US [patent_app_date] => 2023-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18135915 [rel_patent_id] =>[rel_patent_doc_number] =>)