Search

Daniel J. Wiley

Examiner (ID: 7827, Phone: (571)270-7324 , Office: P/3679 )

Most Active Art Unit
3678
Art Unit(s)
3678, 3679
Total Applications
1207
Issued Applications
906
Pending Applications
65
Abandoned Applications
257

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18698631 [patent_doc_number] => 20230329122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => MRAM MEMORY ARRAY YIELD IMPROVEMENT [patent_app_type] => utility [patent_app_number] => 17/658838 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17658838 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/658838
MRAM memory array yield improvement Apr 11, 2022 Issued
Array ( [id] => 17737750 [patent_doc_number] => 20220223212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => MULTI-STATE PROGRAMMING OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/709102 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709102 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/709102
Multi-state programming of memory cells Mar 29, 2022 Issued
Array ( [id] => 18679518 [patent_doc_number] => 20230317174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => UTILIZING DATA PATTERN EFFECT TO CONTROL READ CLOCK TIMING AND BIT LINE KICK FOR READ TIME REDUCTION [patent_app_type] => utility [patent_app_number] => 17/706993 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706993 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/706993
Utilizing data pattern effect to control read clock timing and bit line kick for read time reduction Mar 28, 2022 Issued
Array ( [id] => 19046471 [patent_doc_number] => 11935590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Device for matrix-vector multiplications [patent_app_type] => utility [patent_app_number] => 17/706695 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6392 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706695 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/706695
Device for matrix-vector multiplications Mar 28, 2022 Issued
Array ( [id] => 18918979 [patent_doc_number] => 11881267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/654136 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 33 [patent_no_of_words] => 15899 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654136 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654136
Semiconductor memory device Mar 8, 2022 Issued
Array ( [id] => 17870451 [patent_doc_number] => 20220293188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SEMICONDUCTOR MEMORY DEVICE WITH WRITE DISTURB REDUCTION [patent_app_type] => utility [patent_app_number] => 17/685133 [patent_app_country] => US [patent_app_date] => 2022-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685133
Semiconductor memory device with write disturb reduction Mar 1, 2022 Issued
Array ( [id] => 19610807 [patent_doc_number] => 12159687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Clock circuit, memory and method for manufacturing semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/651624 [patent_app_country] => US [patent_app_date] => 2022-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5316 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17651624 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/651624
Clock circuit, memory and method for manufacturing semiconductor structure Feb 17, 2022 Issued
Array ( [id] => 18935243 [patent_doc_number] => 11887681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Performing selective copyback in memory devices [patent_app_type] => utility [patent_app_number] => 17/675477 [patent_app_country] => US [patent_app_date] => 2022-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10520 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17675477 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/675477
Performing selective copyback in memory devices Feb 17, 2022 Issued
Array ( [id] => 18239261 [patent_doc_number] => 20230071572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => ADDRESS LATCH, ADDRESS CONTROL CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE ADDRESS CONTROL CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/672069 [patent_app_country] => US [patent_app_date] => 2022-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672069 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/672069
Address latch, address control circuit and semiconductor apparatus including the address control circuit Feb 14, 2022 Issued
Array ( [id] => 18335554 [patent_doc_number] => 20230127502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => MEMORY CELL AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/586585 [patent_app_country] => US [patent_app_date] => 2022-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17586585 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/586585
Memory cell and method of operating the same Jan 26, 2022 Issued
Array ( [id] => 19413336 [patent_doc_number] => 12079152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Systems and methods of testing memory devices [patent_app_type] => utility [patent_app_number] => 17/585352 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 15075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585352 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/585352
Systems and methods of testing memory devices Jan 25, 2022 Issued
Array ( [id] => 18593123 [patent_doc_number] => 11742032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/583488 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9466 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 432 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17583488 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/583488
Semiconductor memory device Jan 24, 2022 Issued
Array ( [id] => 18531856 [patent_doc_number] => 20230236928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => READ-DISTURB-BASED PHYSICAL STORAGE READ TEMPERATURE INFORMATION IDENTIFICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 17/581874 [patent_app_country] => US [patent_app_date] => 2022-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581874 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/581874
Read-disturb-based physical storage read temperature information identification system Jan 21, 2022 Issued
Array ( [id] => 18514386 [patent_doc_number] => 20230230641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => DATA STORAGE DEVICE HAVING OVER-VOLTAGE DETECTION AND PROTECTION [patent_app_type] => utility [patent_app_number] => 17/579246 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17579246 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/579246
Data storage device having over-voltage detection and protection Jan 18, 2022 Issued
Array ( [id] => 17708283 [patent_doc_number] => 20220208291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => TECHNIQUES FOR PROGRAMMING SELF-SELECTING MEMORY [patent_app_type] => utility [patent_app_number] => 17/573229 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20803 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573229 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573229
Techniques for programming self-selecting memory Jan 10, 2022 Issued
Array ( [id] => 18500309 [patent_doc_number] => 20230223094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => METHODS FOR RECOVERY FOR MEMORY SYSTEMS AND MEMORY SYSTEMS EMPLOYING THE SAME [patent_app_type] => utility [patent_app_number] => 17/571319 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571319 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/571319
Methods for recovery for memory systems and memory systems employing the same Jan 6, 2022 Issued
Array ( [id] => 19137832 [patent_doc_number] => 11972803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Word line zone dependent pre-charge voltage [patent_app_type] => utility [patent_app_number] => 17/571124 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 11304 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571124 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/571124
Word line zone dependent pre-charge voltage Jan 6, 2022 Issued
Array ( [id] => 18124417 [patent_doc_number] => 20230010029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => STORAGE DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/570323 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17570323 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/570323
Storage device and operating method thereof Jan 5, 2022 Issued
Array ( [id] => 17708256 [patent_doc_number] => 20220208264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => SOCKET DESIGN FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/568461 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568461 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568461
Socket design for a memory device Jan 3, 2022 Issued
Array ( [id] => 17551298 [patent_doc_number] => 20220122640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/565713 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17565713 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/565713
Semiconductor device Dec 29, 2021 Issued
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