Search

Daniel Lee Cerioni

Examiner (ID: 680, Phone: (313)446-4818 , Office: P/3736 )

Most Active Art Unit
3791
Art Unit(s)
3791, 3736
Total Applications
866
Issued Applications
472
Pending Applications
148
Abandoned Applications
292

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16516700 [patent_doc_number] => 20200395958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => LDPC CODING WITH DIFFERENTIATED PROTECTION [patent_app_type] => utility [patent_app_number] => 16/897814 [patent_app_country] => US [patent_app_date] => 2020-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16897814 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/897814
LDPC coding with differentiated protection Jun 9, 2020 Issued
Array ( [id] => 18053912 [patent_doc_number] => 11527303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Memory devices having variable repair units therein and methods of repairing same [patent_app_type] => utility [patent_app_number] => 16/890559 [patent_app_country] => US [patent_app_date] => 2020-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 9658 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16890559 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/890559
Memory devices having variable repair units therein and methods of repairing same Jun 1, 2020 Issued
Array ( [id] => 17151332 [patent_doc_number] => 11144410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => System and method to dynamically increase memory channel robustness at high transfer rates [patent_app_type] => utility [patent_app_number] => 16/874380 [patent_app_country] => US [patent_app_date] => 2020-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874380 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/874380
System and method to dynamically increase memory channel robustness at high transfer rates May 13, 2020 Issued
Array ( [id] => 17544774 [patent_doc_number] => 11309915 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-19 [patent_title] => Efficient implementation of a threshold modified min-sum algorithm for low-density parity-check decoders [patent_app_type] => utility [patent_app_number] => 16/872106 [patent_app_country] => US [patent_app_date] => 2020-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6382 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16872106 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/872106
Efficient implementation of a threshold modified min-sum algorithm for low-density parity-check decoders May 10, 2020 Issued
Array ( [id] => 17773098 [patent_doc_number] => 11405056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Magic state distillation using inner and outer error correcting codes [patent_app_type] => utility [patent_app_number] => 16/870988 [patent_app_country] => US [patent_app_date] => 2020-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10411 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16870988 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/870988
Magic state distillation using inner and outer error correcting codes May 9, 2020 Issued
Array ( [id] => 18401373 [patent_doc_number] => 11663511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Iterative quantum amplitude estimation [patent_app_type] => utility [patent_app_number] => 16/866108 [patent_app_country] => US [patent_app_date] => 2020-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16866108 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/866108
Iterative quantum amplitude estimation May 3, 2020 Issued
Array ( [id] => 17682465 [patent_doc_number] => 11366718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Optimal read bias tracking system and method thereof [patent_app_type] => utility [patent_app_number] => 16/863368 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8432 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16863368 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/863368
Optimal read bias tracking system and method thereof Apr 29, 2020 Issued
Array ( [id] => 17515615 [patent_doc_number] => 11294765 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-05 [patent_title] => Resolving write conflicts in a dispersed storage network [patent_app_type] => utility [patent_app_number] => 16/860883 [patent_app_country] => US [patent_app_date] => 2020-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8541 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16860883 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/860883
Resolving write conflicts in a dispersed storage network Apr 27, 2020 Issued
Array ( [id] => 19494901 [patent_doc_number] => 12113628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Hybrid automatic repeat request (ARQ) with spatial diversity [patent_app_type] => utility [patent_app_number] => 17/920490 [patent_app_country] => US [patent_app_date] => 2020-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17920490 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/920490
Hybrid automatic repeat request (ARQ) with spatial diversity Apr 23, 2020 Issued
Array ( [id] => 16425729 [patent_doc_number] => 20200350927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => APPARATUS AND METHOD FOR DECODING OF LOW-DENSITY PARITY CHECK CODES IN WIRELESS COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 16/855524 [patent_app_country] => US [patent_app_date] => 2020-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16855524 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/855524
Apparatus and method for decoding of low-density parity check codes in wireless communication system Apr 21, 2020 Issued
Array ( [id] => 17180114 [patent_doc_number] => 11157357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Operation methods of memory system and host, and computing system [patent_app_type] => utility [patent_app_number] => 16/855000 [patent_app_country] => US [patent_app_date] => 2020-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10078 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16855000 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/855000
Operation methods of memory system and host, and computing system Apr 21, 2020 Issued
Array ( [id] => 17623867 [patent_doc_number] => 11342936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Data processing device and data processing method [patent_app_type] => utility [patent_app_number] => 16/854497 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 132 [patent_figures_cnt] => 140 [patent_no_of_words] => 52134 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 1080 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854497 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/854497
Data processing device and data processing method Apr 20, 2020 Issued
Array ( [id] => 17254790 [patent_doc_number] => 11190299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Ethernet communication apparatus, and method for recovering error of end node and switch in vehicle [patent_app_type] => utility [patent_app_number] => 16/854204 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 11537 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854204 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/854204
Ethernet communication apparatus, and method for recovering error of end node and switch in vehicle Apr 20, 2020 Issued
Array ( [id] => 16722247 [patent_doc_number] => 20210089394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => STORAGE DEVICE SELECTIVELY GENERATING PARITY BITS ACCORDING TO ENDURANCE OF MEMORY CELL, AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/851434 [patent_app_country] => US [patent_app_date] => 2020-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16851434 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/851434
Storage device selectively generating parity bits according to endurance of memory cell, and method thereof Apr 16, 2020 Issued
Array ( [id] => 18670613 [patent_doc_number] => 11777531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Method and apparatus for high-speed decoding of linear code on basis of soft decision [patent_app_type] => utility [patent_app_number] => 17/609994 [patent_app_country] => US [patent_app_date] => 2020-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 9183 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17609994 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/609994
Method and apparatus for high-speed decoding of linear code on basis of soft decision Apr 13, 2020 Issued
Array ( [id] => 17379885 [patent_doc_number] => 11237901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Error correction using hierarchical decoders [patent_app_type] => utility [patent_app_number] => 16/834198 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834198 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/834198
Error correction using hierarchical decoders Mar 29, 2020 Issued
Array ( [id] => 16181173 [patent_doc_number] => 20200228142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => Shift Values for Quasi-Cyclic LDPC Codes [patent_app_type] => utility [patent_app_number] => 16/834624 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834624 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/834624
Shift values for quasi-cyclic LDPC codes Mar 29, 2020 Issued
Array ( [id] => 17863474 [patent_doc_number] => 11444639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Method and system for polar code coding [patent_app_type] => utility [patent_app_number] => 16/830968 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7265 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16830968 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/830968
Method and system for polar code coding Mar 25, 2020 Issued
Array ( [id] => 16160481 [patent_doc_number] => 20200218473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/826595 [patent_app_country] => US [patent_app_date] => 2020-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15001 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 429 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16826595 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/826595
Memory system Mar 22, 2020 Issued
Array ( [id] => 16623536 [patent_doc_number] => 20210042189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => METHODS FOR ERROR DETECTION AND CORRECTION AND CORRESPONDING SYSTEMS AND DEVICES FOR THE SAME [patent_app_type] => utility [patent_app_number] => 16/826998 [patent_app_country] => US [patent_app_date] => 2020-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16826998 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/826998
Methods for error detection and correction and corresponding systems and devices for the same Mar 22, 2020 Issued
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