Daniel M. Luke

Array ( [id] => 16873504 [patent_doc_number] => 20210166971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => ZINCATING AND DOPING OF METAL LINER FOR LINER PASSIVATION AND ADHESION IMPROVEMENT [patent_app_type] => utility [patent_app_number] => 17/257207 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17257207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16896545 [patent_doc_number] => 11038108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Step height mitigation in resistive random access memory structures [patent_app_type] => utility [patent_app_number] => 16/422207 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15657327 [patent_doc_number] => 20200091194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => DISPLAY SUBSTRATE, METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/422074 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4010 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17254109 [patent_doc_number] => 11189607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Transparent micro LED display panel [patent_app_type] => utility [patent_app_number] => 16/421848 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2632 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16973620 [patent_doc_number] => 11069600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Semiconductor package with space efficient lead and die pad design [patent_app_type] => utility [patent_app_number] => 16/422163 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 6 [patent_no_of_words] => 6156 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422163 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15218121 [patent_doc_number] => 20190371747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => LAUNCH STRUCTURES FOR RADIO FREQUENCY INTEGRATED DEVICE PACKAGES [patent_app_type] => utility [patent_app_number] => 16/421221 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17166324 [patent_doc_number] => 11152437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Display apparatus having self-aligned structures and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/420930 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 5639 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17166197 [patent_doc_number] => 11152309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Semiconductor package, method of fabricating semiconductor package, and method of fabricating redistribution structure [patent_app_type] => utility [patent_app_number] => 16/411586 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 7492 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15547939 [patent_doc_number] => 10573762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Vertical gallium nitride Schottky diode [patent_app_type] => utility [patent_app_number] => 16/397720 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 34 [patent_no_of_words] => 8127 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16397720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14691411 [patent_doc_number] => 20190244821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/385161 [patent_app_country] => US [patent_app_date] => 2019-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16385161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16379301 [patent_doc_number] => 20200328144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/382229 [patent_app_country] => US [patent_app_date] => 2019-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7431 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16382229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17326486 [patent_doc_number] => 11217511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Quad package with conductive clips connected to terminals at upper surface of semiconductor die [patent_app_type] => utility [patent_app_number] => 16/379405 [patent_app_country] => US [patent_app_date] => 2019-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 5933 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16379405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16364525 [patent_doc_number] => 20200321276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => Chip to Chip Interconnect in Encapsulant of Molded Semiconductor Package [patent_app_type] => utility [patent_app_number] => 16/375479 [patent_app_country] => US [patent_app_date] => 2019-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16375479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15442835 [patent_doc_number] => 20200035601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => SEMICONDUCTOR DEVICE HAVING SYMMETRIC CONDUCTIVE INTERCONNECTION PATTERNS [patent_app_type] => utility [patent_app_number] => 16/358661 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -37 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16332373 [patent_doc_number] => 20200303339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => LEAD-FREE COLUMN INTERCONNECT [patent_app_type] => utility [patent_app_number] => 16/358658 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16301152 [patent_doc_number] => 20200286875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => THREE-DIMENSIONAL DEVICE WITH BONDED STRUCTURES INCLUDING A SUPPORT DIE AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/291504 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16301052 [patent_doc_number] => 20200286775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => INTERCONNECT STRUCTURE AND METHOD FOR PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 16/291376 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14843049 [patent_doc_number] => 20190279925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/291065 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14350805 [patent_doc_number] => 20190157375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/255821 [patent_app_country] => US [patent_app_date] => 2019-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16255821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16001095 [patent_doc_number] => 20200176418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => DUAL-DIE MEMORY PACKAGE [patent_app_type] => utility [patent_app_number] => 16/254599 [patent_app_country] => US [patent_app_date] => 2019-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16254599 [rel_patent_id] =>[rel_patent_doc_number] =>)