Search

Daniel M. Luke

Examiner (ID: 10322, Phone: (571)270-1569 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813, 2896
Total Applications
866
Issued Applications
580
Pending Applications
69
Abandoned Applications
228

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14753097 [patent_doc_number] => 20190259722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => COPPER PILLARS HAVING IMPROVED INTEGRITY AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/255124 [patent_app_country] => US [patent_app_date] => 2019-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16255124 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/255124
COPPER PILLARS HAVING IMPROVED INTEGRITY AND METHODS OF MAKING THE SAME Jan 22, 2019 Abandoned
Array ( [id] => 15889805 [patent_doc_number] => 10651259 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Display device with transparent capacitor [patent_app_type] => utility [patent_app_number] => 16/251747 [patent_app_country] => US [patent_app_date] => 2019-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6511 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16251747 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/251747
Display device with transparent capacitor Jan 17, 2019 Issued
Array ( [id] => 16928320 [patent_doc_number] => 11049811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Forming interlayer dielectric material by spin-on metal oxide deposition [patent_app_type] => utility [patent_app_number] => 16/232921 [patent_app_country] => US [patent_app_date] => 2018-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16232921 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/232921
Forming interlayer dielectric material by spin-on metal oxide deposition Dec 25, 2018 Issued
Array ( [id] => 15286469 [patent_doc_number] => 10515904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Method for forming chip package structure [patent_app_type] => utility [patent_app_number] => 16/229021 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 6405 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229021 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/229021
Method for forming chip package structure Dec 20, 2018 Issued
Array ( [id] => 15154821 [patent_doc_number] => 20190355888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => LIGHT EMITTING CHIP AND ASSOCIATED PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/221891 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16221891 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/221891
LIGHT EMITTING CHIP AND ASSOCIATED PACKAGE STRUCTURE Dec 16, 2018 Abandoned
Array ( [id] => 16835248 [patent_doc_number] => 11011508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Dielectric spaced diode [patent_app_type] => utility [patent_app_number] => 16/220881 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 6602 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220881 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/220881
Dielectric spaced diode Dec 13, 2018 Issued
Array ( [id] => 16080871 [patent_doc_number] => 20200194422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => DIELECTRIC SPACED DIODE [patent_app_type] => utility [patent_app_number] => 16/220793 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9331 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220793 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/220793
Dielectric spaced diode Dec 13, 2018 Issued
Array ( [id] => 16894552 [patent_doc_number] => 11036100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 16/181380 [patent_app_country] => US [patent_app_date] => 2018-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 6802 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181380 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/181380
Display device Nov 5, 2018 Issued
Array ( [id] => 14285267 [patent_doc_number] => 20190139918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 16/181383 [patent_app_country] => US [patent_app_date] => 2018-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181383 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/181383
Semiconductor device bonding area including fused solder film and manufacturing method Nov 5, 2018 Issued
Array ( [id] => 14938513 [patent_doc_number] => 20190304895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/181739 [patent_app_country] => US [patent_app_date] => 2018-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181739 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/181739
Semiconductor device with air gaps in interlayer insulating layer and method of manufacturing the same Nov 5, 2018 Issued
Array ( [id] => 15260151 [patent_doc_number] => 20190378809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => Semiconductor Packages and Method Forming Same [patent_app_type] => utility [patent_app_number] => 16/157426 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157426 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/157426
Method for manufacturing semiconductor package with connection structures including via groups Oct 10, 2018 Issued
Array ( [id] => 16759831 [patent_doc_number] => 10978388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Skip via for metal interconnects [patent_app_type] => utility [patent_app_number] => 16/153901 [patent_app_country] => US [patent_app_date] => 2018-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5976 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16153901 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/153901
Skip via for metal interconnects Oct 7, 2018 Issued
Array ( [id] => 16738973 [patent_doc_number] => 10964639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Integrated circuits including via array and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/153153 [patent_app_country] => US [patent_app_date] => 2018-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12284 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16153153 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/153153
Integrated circuits including via array and methods of manufacturing the same Oct 4, 2018 Issued
Array ( [id] => 14812911 [patent_doc_number] => 20190273065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => MEMORY PACKAGE AND MEMORY DEVICE UTILIZING AN INTERMEDIATE CHIP [patent_app_type] => utility [patent_app_number] => 16/150926 [patent_app_country] => US [patent_app_date] => 2018-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6753 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16150926 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/150926
Memory package and memory device utilizing an intermediate chip Oct 2, 2018 Issued
Array ( [id] => 15625519 [patent_doc_number] => 20200083164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => SELECTIVE DEPOSITION OF EMBEDDED THIN-FILM RESISTORS FOR SEMICONDUCTOR PACKAGING [patent_app_type] => utility [patent_app_number] => 16/129711 [patent_app_country] => US [patent_app_date] => 2018-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16129711 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/129711
Selective deposition of embedded thin-film resistors for semiconductor packaging Sep 11, 2018 Issued
Array ( [id] => 13785599 [patent_doc_number] => 20190006338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => ISOLATOR INTEGRATED CIRCUITS WITH PACKAGE STRUCTURE CAVITY AND FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 16/126577 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/126577
Isolator integrated circuits with package structure cavity and fabrication methods Sep 9, 2018 Issued
Array ( [id] => 14738999 [patent_doc_number] => 10388913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Organic light emitting display device [patent_app_type] => utility [patent_app_number] => 16/125229 [patent_app_country] => US [patent_app_date] => 2018-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9061 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16125229 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/125229
Organic light emitting display device Sep 6, 2018 Issued
Array ( [id] => 13829113 [patent_doc_number] => 20190018041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => NANOTUBE BASED TRANSISTOR STRUCTURE, METHOD OF FABRICATION AND USES THEREOF [patent_app_type] => utility [patent_app_number] => 16/120375 [patent_app_country] => US [patent_app_date] => 2018-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16120375 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/120375
NANOTUBE BASED TRANSISTOR STRUCTURE, METHOD OF FABRICATION AND USES THEREOF Sep 2, 2018 Abandoned
Array ( [id] => 16280405 [patent_doc_number] => 10763448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => OLED device with buffer layer adjacent light emitting layer [patent_app_type] => utility [patent_app_number] => 16/117781 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5446 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117781 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117781
OLED device with buffer layer adjacent light emitting layer Aug 29, 2018 Issued
Array ( [id] => 16835318 [patent_doc_number] => 11011579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Cross-point memory and methods for fabrication of same [patent_app_type] => utility [patent_app_number] => 16/112476 [patent_app_country] => US [patent_app_date] => 2018-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7945 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16112476 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/112476
Cross-point memory and methods for fabrication of same Aug 23, 2018 Issued
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