Search

Daniel M. Luke

Examiner (ID: 10322, Phone: (571)270-1569 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813, 2896
Total Applications
866
Issued Applications
580
Pending Applications
69
Abandoned Applications
228

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15139327 [patent_doc_number] => 10483149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Wafer processing method for dividing a wafer, including a shield tunnel forming step [patent_app_type] => utility [patent_app_number] => 16/059238 [patent_app_country] => US [patent_app_date] => 2018-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4582 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16059238 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/059238
Wafer processing method for dividing a wafer, including a shield tunnel forming step Aug 8, 2018 Issued
Array ( [id] => 13570985 [patent_doc_number] => 20180337040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => Treatment to Control Deposition Rate [patent_app_type] => utility [patent_app_number] => 16/051064 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16051064 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/051064
Treatment to control deposition rate Jul 30, 2018 Issued
Array ( [id] => 16133055 [patent_doc_number] => 10700299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Method for manufacturing organic light emitting diode using conductive protective layer [patent_app_type] => utility [patent_app_number] => 16/051286 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5654 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16051286 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/051286
Method for manufacturing organic light emitting diode using conductive protective layer Jul 30, 2018 Issued
Array ( [id] => 16324150 [patent_doc_number] => 10784122 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Method of producing electroconductive substrate, electronic device and display device [patent_app_type] => utility [patent_app_number] => 16/038711 [patent_app_country] => US [patent_app_date] => 2018-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 31 [patent_no_of_words] => 11122 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16038711 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/038711
Method of producing electroconductive substrate, electronic device and display device Jul 17, 2018 Issued
Array ( [id] => 16068157 [patent_doc_number] => 10693045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Method for attaching light transmissive member to light emitting element for manufacturing light emitting device [patent_app_type] => utility [patent_app_number] => 16/037763 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 6538 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037763 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/037763
Method for attaching light transmissive member to light emitting element for manufacturing light emitting device Jul 16, 2018 Issued
Array ( [id] => 16372673 [patent_doc_number] => 10804439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Method of producing a plurality of conversion elements and optoelectronic component [patent_app_type] => utility [patent_app_number] => 16/037388 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 4641 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037388 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/037388
Method of producing a plurality of conversion elements and optoelectronic component Jul 16, 2018 Issued
Array ( [id] => 14351059 [patent_doc_number] => 20190157502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => GROWTH SUBSTRATE INCLUDING MICRO-LIGHT EMITTING DIODE CHIPS AND METHOD OF MANUFACTURING LIGHT EMITTING DIODE DISPLAY USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/037174 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7224 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037174 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/037174
Growth substrate including micro-light emitting diode chips and method of manufacturing light emitting diode display using the same Jul 16, 2018 Issued
Array ( [id] => 13582209 [patent_doc_number] => 20180342653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING CONDUCTIVE ADHESIVE AND SEMICONDUCTOR DEVICE FABRICATED BY THE SAME [patent_app_type] => utility [patent_app_number] => 16/034963 [patent_app_country] => US [patent_app_date] => 2018-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16034963 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/034963
METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING CONDUCTIVE ADHESIVE AND SEMICONDUCTOR DEVICE FABRICATED BY THE SAME Jul 12, 2018 Abandoned
Array ( [id] => 15369623 [patent_doc_number] => 20200020576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/033179 [patent_app_country] => US [patent_app_date] => 2018-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033179 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/033179
Forming contact holes using litho-etch-litho-etch approach Jul 10, 2018 Issued
Array ( [id] => 15375789 [patent_doc_number] => 10529622 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-07 [patent_title] => Void-free metallic interconnect structures with self-formed diffusion barrier layers [patent_app_type] => utility [patent_app_number] => 16/031059 [patent_app_country] => US [patent_app_date] => 2018-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 7807 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16031059 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/031059
Void-free metallic interconnect structures with self-formed diffusion barrier layers Jul 9, 2018 Issued
Array ( [id] => 15286265 [patent_doc_number] => 10515802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Techniques for forming low stress mask using implantation [patent_app_type] => utility [patent_app_number] => 16/030311 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 5698 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030311 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030311
Techniques for forming low stress mask using implantation Jul 8, 2018 Issued
Array ( [id] => 13543537 [patent_doc_number] => 20180323315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => TERMINATION STRUCTURE FOR GALLIUM NITRIDE SCHOTTKY DIODE INCLUDING JUNCTION BARRIAR DIODES [patent_app_type] => utility [patent_app_number] => 16/019085 [patent_app_country] => US [patent_app_date] => 2018-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16019085 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/019085
Termination structure for gallium nitride Schottky diode including junction barriar diodes Jun 25, 2018 Issued
Array ( [id] => 13571141 [patent_doc_number] => 20180337118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => Interconnection Substrates for Interconnection Between Circuit Modules, and Methods of Manufacture [patent_app_type] => utility [patent_app_number] => 16/017010 [patent_app_country] => US [patent_app_date] => 2018-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16017010 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/017010
Interconnection substrates for interconnection between circuit modules, and methods of manufacture Jun 24, 2018 Issued
Array ( [id] => 13485573 [patent_doc_number] => 20180294329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => METAL RESISTORS HAVING NITRIDIZED DIELECTRIC SURFACE LAYERS AND NITRIDIZED METAL SURFACE LAYERS [patent_app_type] => utility [patent_app_number] => 16/004103 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16004103 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/004103
Metal resistors having nitridized dielectric surface layers and nitridized metal surface layers Jun 7, 2018 Issued
Array ( [id] => 13435411 [patent_doc_number] => 20180269248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 15/987278 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987278 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987278
Semiconductor device with multiple substrates electrically connected through an insulating film May 22, 2018 Issued
Array ( [id] => 13364197 [patent_doc_number] => 20180233638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => LIGHT EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 15/953082 [patent_app_country] => US [patent_app_date] => 2018-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15953082 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/953082
Method of manufacturing light emitting device with light-transmissive members Apr 12, 2018 Issued
Array ( [id] => 18688512 [patent_doc_number] => 11784258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Thin film transistor with insulating portion between source/drian electrode and gate insulating layer, and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/309786 [patent_app_country] => US [patent_app_date] => 2018-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 5600 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16309786 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/309786
Thin film transistor with insulating portion between source/drian electrode and gate insulating layer, and manufacturing method thereof Apr 3, 2018 Issued
Array ( [id] => 14125677 [patent_doc_number] => 10249703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Metal resistors having nitridized metal surface layers with different nitrogen content [patent_app_type] => utility [patent_app_number] => 15/935942 [patent_app_country] => US [patent_app_date] => 2018-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15935942 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/935942
Metal resistors having nitridized metal surface layers with different nitrogen content Mar 25, 2018 Issued
Array ( [id] => 12918295 [patent_doc_number] => 20180197941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => METAL RESISTORS HAVING VARYING RESISTIVITY [patent_app_type] => utility [patent_app_number] => 15/914106 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914106 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/914106
Metal resistors having varying resistivity Mar 6, 2018 Issued
Array ( [id] => 15315385 [patent_doc_number] => 10522406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => IR assisted fan-out wafer level packaging using silicon handler [patent_app_type] => utility [patent_app_number] => 15/903973 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 6426 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15903973 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/903973
IR assisted fan-out wafer level packaging using silicon handler Feb 22, 2018 Issued
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