Daniel M. Luke

Array ( [id] => 13243167 [patent_doc_number] => 10134795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Semiconductor device with multiple substrates electrically connected through an insulating film and manufacturing method [patent_app_type] => utility [patent_app_number] => 15/607845 [patent_app_country] => US [patent_app_date] => 2017-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 9085 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15607845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11959725 [patent_doc_number] => 20170263878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'Light-Emitting Element, Light-Emitting Device, Electronic Device, and Lighting Device' [patent_app_type] => utility [patent_app_number] => 15/602450 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 21985 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15602450 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14397607 [patent_doc_number] => 10312094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => AlO [patent_app_type] => utility [patent_app_number] => 15/600260 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 39 [patent_no_of_words] => 8124 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15600260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11946098 [patent_doc_number] => 20170250249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'Method of Forming Ultra-Thin Nanowires' [patent_app_type] => utility [patent_app_number] => 15/595253 [patent_app_country] => US [patent_app_date] => 2017-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15595253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12054458 [patent_doc_number] => 20170330801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'METHOD OF FORMING GATE OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE HAVING SAME' [patent_app_type] => utility [patent_app_number] => 15/591944 [patent_app_country] => US [patent_app_date] => 2017-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11688 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15591944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12032807 [patent_doc_number] => 20170322906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'Processor with In-Package Look-Up Table' [patent_app_type] => utility [patent_app_number] => 15/587359 [patent_app_country] => US [patent_app_date] => 2017-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3816 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15587359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12990589 [patent_doc_number] => 20170345942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => THIN-FILM TRANSISTOR, DISPLAY UNIT, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 15/584008 [patent_app_country] => US [patent_app_date] => 2017-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15584008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17878512 [patent_doc_number] => 11450535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Manufacturing method for semiconductor package including filling member and membrane member [patent_app_type] => utility [patent_app_number] => 16/090602 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6547 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16090602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16394453 [patent_doc_number] => 20200335394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => METHOD OF MANUFACTURING SUBSTRATE AND THE SAME SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/090059 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16090059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12122562 [patent_doc_number] => 20180006148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'LDMOS TRANSISTOR AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/436905 [patent_app_country] => US [patent_app_date] => 2017-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15436905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13833275 [patent_doc_number] => 20190020122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => Inkjet Printed Flexible Van Atta Array Sensor [patent_app_type] => utility [patent_app_number] => 16/069440 [patent_app_country] => US [patent_app_date] => 2017-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16069440 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12554058 [patent_doc_number] => 10014243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Interconnection substrates for interconnection between circuit modules, and methods of manufacture [patent_app_type] => utility [patent_app_number] => 15/403679 [patent_app_country] => US [patent_app_date] => 2017-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5581 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15403679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11718317 [patent_doc_number] => 20170186816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME' [patent_app_type] => utility [patent_app_number] => 15/398475 [patent_app_country] => US [patent_app_date] => 2017-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8415 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15398475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12692824 [patent_doc_number] => 20180122774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => Redistribution Layers in Semiconductor Packages and Methods of Forming Same [patent_app_type] => utility [patent_app_number] => 15/396208 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9456 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12896359 [patent_doc_number] => 20180190628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => ISOLATOR INTEGRATED CIRCUITS WITH PACKAGE STRUCTURE CAVITY AND FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 15/395584 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6303 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11571720 [patent_doc_number] => 20170110364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'REVERSE SELF ALIGNED DOUBLE PATTERNING PROCESS FOR BACK END OF LINE FABRICATION OF A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/390405 [patent_app_country] => US [patent_app_date] => 2016-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15394 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15390405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11840284 [patent_doc_number] => 20170222004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'SEMICONDUCTOR DEVICE AND TRANSMITTER' [patent_app_type] => utility [patent_app_number] => 15/386025 [patent_app_country] => US [patent_app_date] => 2016-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7242 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15386025 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15873299 [patent_doc_number] => 20200144053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/316120 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16316120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12738967 [patent_doc_number] => 20180138156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => CLIPS DEFINING ELECTRICAL PATHWAY ON A FLEXIBLE SHEET [patent_app_type] => utility [patent_app_number] => 15/354790 [patent_app_country] => US [patent_app_date] => 2016-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3675 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15354790 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12314331 [patent_doc_number] => 09941162 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-10 [patent_title] => Self-aligned middle of the line (MOL) contacts [patent_app_type] => utility [patent_app_number] => 15/354212 [patent_app_country] => US [patent_app_date] => 2016-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 40 [patent_no_of_words] => 10620 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15354212 [rel_patent_id] =>[rel_patent_doc_number] =>)