Search

Daniel M. Luke

Examiner (ID: 2133, Phone: (571)270-1569 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813, 2896
Total Applications
848
Issued Applications
566
Pending Applications
72
Abandoned Applications
226

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10343724 [patent_doc_number] => 20150228729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'PROTECTION CIRCUIT INCLUDING VERTICAL GALLIUM NITRIDE SCHOTTKY DIODE AND SCHOTTKY DIODE' [patent_app_type] => utility [patent_app_number] => 14/632352 [patent_app_country] => US [patent_app_date] => 2015-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 7010 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14632352 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/632352
Protection circuit including vertical gallium nitride schottky diode and PN junction diode Feb 25, 2015 Issued
Array ( [id] => 10286167 [patent_doc_number] => 20150171165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'BONDED STRAINED SEMICONDUCTOR WITH A DESIRED SURFACE ORIENTATION AND CONDUCTANCE DIRECTION' [patent_app_type] => utility [patent_app_number] => 14/628825 [patent_app_country] => US [patent_app_date] => 2015-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14628825 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/628825
BONDED STRAINED SEMICONDUCTOR WITH A DESIRED SURFACE ORIENTATION AND CONDUCTANCE DIRECTION Feb 22, 2015 Abandoned
Array ( [id] => 10252069 [patent_doc_number] => 20150137064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'Reduction of forming voltage in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/595421 [patent_app_country] => US [patent_app_date] => 2015-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13496 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14595421 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/595421
Reduction of forming voltage in semiconductor devices Jan 12, 2015 Issued
Array ( [id] => 10238207 [patent_doc_number] => 20150123201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'Strained Semiconductor Device and Method of Making the Same' [patent_app_type] => utility [patent_app_number] => 14/595977 [patent_app_country] => US [patent_app_date] => 2015-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4520 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14595977 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/595977
Strained semiconductor device and method of making the same Jan 12, 2015 Issued
Array ( [id] => 10226318 [patent_doc_number] => 20150111310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/590117 [patent_app_country] => US [patent_app_date] => 2015-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 10101 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14590117 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/590117
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Jan 5, 2015 Abandoned
Array ( [id] => 10206157 [patent_doc_number] => 20150091145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'Semiconductor Device and Method of Forming Conductive Vias Through Interconnect Structures and Encapsulant of WLCSP' [patent_app_type] => utility [patent_app_number] => 14/566870 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5514 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14566870 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/566870
Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSP Dec 10, 2014 Issued
Array ( [id] => 9917250 [patent_doc_number] => 20150072455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'METHOD FOR FABRICATING LIGHT EMITTING DIODE (LED) DICE WITH WAVELENGTH CONVERSION LAYERS' [patent_app_type] => utility [patent_app_number] => 14/541200 [patent_app_country] => US [patent_app_date] => 2014-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2976 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14541200 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/541200
Method for fabricating light emitting diode (LED) dice with wavelength conversion layers Nov 13, 2014 Issued
Array ( [id] => 10557171 [patent_doc_number] => 09281377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Semiconductor device having silicide on gate sidewalls in isolation regions' [patent_app_type] => utility [patent_app_number] => 14/535851 [patent_app_country] => US [patent_app_date] => 2014-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 4903 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14535851 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/535851
Semiconductor device having silicide on gate sidewalls in isolation regions Nov 6, 2014 Issued
Array ( [id] => 13099491 [patent_doc_number] => 10069094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-04 [patent_title] => Nanotube based transistor structure, method of fabrication and uses thereof [patent_app_type] => utility [patent_app_number] => 15/034186 [patent_app_country] => US [patent_app_date] => 2014-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 11249 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15034186 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/034186
Nanotube based transistor structure, method of fabrication and uses thereof Nov 5, 2014 Issued
Array ( [id] => 10238224 [patent_doc_number] => 20150123219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'ELECTRODE SYSTEM FOR A MICROMECHANICAL COMPONENT' [patent_app_type] => utility [patent_app_number] => 14/533777 [patent_app_country] => US [patent_app_date] => 2014-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4280 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14533777 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/533777
ELECTRODE SYSTEM FOR A MICROMECHANICAL COMPONENT Nov 4, 2014 Abandoned
Array ( [id] => 11466786 [patent_doc_number] => 09583426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Multi-layer substrates suitable for interconnection between circuit modules' [patent_app_type] => utility [patent_app_number] => 14/533728 [patent_app_country] => US [patent_app_date] => 2014-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 6000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14533728 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/533728
Multi-layer substrates suitable for interconnection between circuit modules Nov 4, 2014 Issued
Array ( [id] => 10502808 [patent_doc_number] => 09231211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Method for forming a multicolor OLED device' [patent_app_type] => utility [patent_app_number] => 14/524371 [patent_app_country] => US [patent_app_date] => 2014-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 35 [patent_no_of_words] => 14797 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14524371 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/524371
Method for forming a multicolor OLED device Oct 26, 2014 Issued
Array ( [id] => 11227624 [patent_doc_number] => 09455349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'Oxide semiconductor thin film transistor with reduced impurity diffusion' [patent_app_type] => utility [patent_app_number] => 14/518259 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 80 [patent_no_of_words] => 36088 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518259 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/518259
Oxide semiconductor thin film transistor with reduced impurity diffusion Oct 19, 2014 Issued
Array ( [id] => 12019874 [patent_doc_number] => 09812586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Transistor with curved active layer' [patent_app_type] => utility [patent_app_number] => 14/518237 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 83 [patent_no_of_words] => 37734 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518237 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/518237
Transistor with curved active layer Oct 19, 2014 Issued
Array ( [id] => 12019874 [patent_doc_number] => 09812586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Transistor with curved active layer' [patent_app_type] => utility [patent_app_number] => 14/518237 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 83 [patent_no_of_words] => 37734 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518237 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/518237
Transistor with curved active layer Oct 19, 2014 Issued
Array ( [id] => 12019874 [patent_doc_number] => 09812586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Transistor with curved active layer' [patent_app_type] => utility [patent_app_number] => 14/518237 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 83 [patent_no_of_words] => 37734 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518237 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/518237
Transistor with curved active layer Oct 19, 2014 Issued
Array ( [id] => 12019874 [patent_doc_number] => 09812586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Transistor with curved active layer' [patent_app_type] => utility [patent_app_number] => 14/518237 [patent_app_country] => US [patent_app_date] => 2014-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 83 [patent_no_of_words] => 37734 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518237 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/518237
Transistor with curved active layer Oct 19, 2014 Issued
Array ( [id] => 10502551 [patent_doc_number] => 09230953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'ESD protection device' [patent_app_type] => utility [patent_app_number] => 14/516978 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 5631 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14516978 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/516978
ESD protection device Oct 16, 2014 Issued
Array ( [id] => 11201193 [patent_doc_number] => 09431414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Vertical memory devices and methods of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/517025 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9919 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517025 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/517025
Vertical memory devices and methods of manufacturing the same Oct 16, 2014 Issued
Array ( [id] => 10563575 [patent_doc_number] => 09287256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Semiconductor device including a separation region formed around a first circuit region' [patent_app_type] => utility [patent_app_number] => 14/517657 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7518 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517657 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/517657
Semiconductor device including a separation region formed around a first circuit region Oct 16, 2014 Issued
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