Search

Daniel M. Luke

Examiner (ID: 10322, Phone: (571)270-1569 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813, 2896
Total Applications
866
Issued Applications
580
Pending Applications
69
Abandoned Applications
228

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18905983 [patent_doc_number] => 20240021468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => DEVICES WITH REDUCED CAPACITANCES [patent_app_type] => utility [patent_app_number] => 18/446217 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7058 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446217 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446217
Devices with reduced capacitances Aug 7, 2023 Issued
Array ( [id] => 20996954 [patent_doc_number] => 12745616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-22 [patent_title] => Semiconductor structure including lines of different height [patent_app_type] => utility [patent_app_number] => 18/366096 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 36 [patent_no_of_words] => 6422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/366096
SEMICONDUCTOR STRUCTURE INCLUDING LINES OF DIFFERENT HEIGHT Aug 6, 2023 Pending
Array ( [id] => 19781499 [patent_doc_number] => 12230537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Semiconductor device structure having air gap and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/230338 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 8839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230338 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230338
Semiconductor device structure having air gap and methods of forming the same Aug 3, 2023 Issued
Array ( [id] => 20540534 [patent_doc_number] => 12557623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Semiconductor device with connecting structure having a doped layer and method for forming the same [patent_app_type] => utility [patent_app_number] => 18/359414 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 5626 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359414 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359414
Semiconductor device with connecting structure having a doped layer and method for forming the same Jul 25, 2023 Issued
Array ( [id] => 19749484 [patent_doc_number] => 20250038049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => INTERCONNECT STRUCTURE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/358525 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358525 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358525
INTERCONNECT STRUCTURE AND FABRICATION METHOD THEREOF Jul 24, 2023 Pending
Array ( [id] => 18943557 [patent_doc_number] => 20240038696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => Apparatus Including a Capacitor and a Coil, and a System Having Such an Apparatus [patent_app_type] => utility [patent_app_number] => 18/225393 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225393 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/225393
Apparatus Including a Capacitor and a Coil, and a System Having Such an Apparatus Jul 23, 2023 Pending
Array ( [id] => 18729342 [patent_doc_number] => 20230343638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/347264 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347264 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347264
Source/drain contact for semiconductor device structure Jul 4, 2023 Issued
Array ( [id] => 19634713 [patent_doc_number] => 20240413162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => CAVITY WITH BOTTOM HAVING DIELECTRIC LAYER PORTION OVER GATE BODY WITHOUT ETCH STOP LAYER AND RELATED METHOD [patent_app_type] => utility [patent_app_number] => 18/332147 [patent_app_country] => US [patent_app_date] => 2023-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332147 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/332147
CAVITY WITH BOTTOM HAVING DIELECTRIC LAYER PORTION OVER GATE BODY WITHOUT ETCH STOP LAYER AND RELATED METHOD Jun 8, 2023 Pending
Array ( [id] => 19559966 [patent_doc_number] => 20240371758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/203655 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203655 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/203655
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME May 30, 2023 Pending
Array ( [id] => 19589822 [patent_doc_number] => 20240387379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => METHOD AND APPARATUS FOR COPPER PLATING IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/318537 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18318537 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/318537
METHOD AND APPARATUS FOR COPPER PLATING IN SEMICONDUCTOR DEVICES May 15, 2023 Pending
Array ( [id] => 19364252 [patent_doc_number] => 20240266286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => SEMICONDUCTOR PATTERN AND METHOD OF ROUNDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/118093 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18118093 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/118093
SEMICONDUCTOR PATTERN AND METHOD OF ROUNDING THE SAME Mar 5, 2023 Pending
Array ( [id] => 18848940 [patent_doc_number] => 20230411344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/175902 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18175902 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/175902
Method for manufacturing semiconductor device Feb 27, 2023 Issued
Array ( [id] => 19407144 [patent_doc_number] => 20240290655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SELECTIVE VIA-FILL WITH CONFORMAL SIDEWALL COVERAGE [patent_app_type] => utility [patent_app_number] => 18/115561 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18115561 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/115561
SELECTIVE VIA-FILL WITH CONFORMAL SIDEWALL COVERAGE Feb 27, 2023 Pending
Array ( [id] => 18439981 [patent_doc_number] => 20230187276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => METHOD OF DIELECTRIC MATERIAL FILL AND TREATMENT [patent_app_type] => utility [patent_app_number] => 18/108338 [patent_app_country] => US [patent_app_date] => 2023-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18108338 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/108338
Method of dielectric material fill and treatment Feb 9, 2023 Issued
Array ( [id] => 20979372 [patent_doc_number] => 12740097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-15 [patent_title] => Structure with isolated well [patent_app_type] => utility [patent_app_number] => 18/104341 [patent_app_country] => US [patent_app_date] => 2023-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104341 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/104341
STRUCTURE WITH ISOLATED WELL Jan 31, 2023 Pending
Array ( [id] => 20760230 [patent_doc_number] => 12653025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => Method of forming semiconductor structure and semiconductor structure [patent_app_type] => utility [patent_app_number] => 18/150275 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 25 [patent_no_of_words] => 3301 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150275 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/150275
Method of forming semiconductor structure and semiconductor structure Jan 4, 2023 Issued
Array ( [id] => 20720231 [patent_doc_number] => 12635503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Graphene coated interconnects with airgap structures [patent_app_type] => utility [patent_app_number] => 18/147731 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18147731 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/147731
Graphene coated interconnects with airgap structures Dec 28, 2022 Issued
Array ( [id] => 19285714 [patent_doc_number] => 20240222191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/089773 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089773 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/089773
Doping barrier layer to facilitate metal fill with large grain size Dec 27, 2022 Issued
Array ( [id] => 20346077 [patent_doc_number] => 12469812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Method for manufacturing semiconductor package with connection structures including via groups [patent_app_type] => utility [patent_app_number] => 18/068088 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 52 [patent_no_of_words] => 3312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18068088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/068088
Method for manufacturing semiconductor package with connection structures including via groups Dec 18, 2022 Issued
Array ( [id] => 20692072 [patent_doc_number] => 12622248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Interconnects with sidewall barrier layer divot fill [patent_app_type] => utility [patent_app_number] => 18/079440 [patent_app_country] => US [patent_app_date] => 2022-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18079440 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/079440
Interconnects with sidewall barrier layer divot fill Dec 11, 2022 Issued
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