Search

Daniel M. Luke

Examiner (ID: 2133, Phone: (571)270-1569 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813, 2896
Total Applications
848
Issued Applications
566
Pending Applications
72
Abandoned Applications
226

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18943526 [patent_doc_number] => 20240038665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => INTERCONNECTION STRUCTURE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/877387 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877387 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/877387
INTERCONNECTION STRUCTURE AND METHOD FOR FABRICATING THE SAME Jul 28, 2022 Pending
Array ( [id] => 18661281 [patent_doc_number] => 20230307294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/813654 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813654 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813654
Metal grinding pretreatment in semiconductor device fabrication method Jul 19, 2022 Issued
Array ( [id] => 17985975 [patent_doc_number] => 20220352012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => VIA STRUCTURE AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/867791 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867791 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/867791
VIA STRUCTURE AND METHODS FOR FORMING THE SAME Jul 18, 2022 Pending
Array ( [id] => 18184410 [patent_doc_number] => 20230045140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => Barrier Schemes for Metallization Using Manganese and Graphene [patent_app_type] => utility [patent_app_number] => 17/864143 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17864143 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/864143
Barrier schemes for metallization using manganese and graphene Jul 12, 2022 Issued
Array ( [id] => 18026383 [patent_doc_number] => 20220377882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => TRANSPARENT PACKAGE FOR USE WITH PRINTED CIRCUIT BOARDS [patent_app_type] => utility [patent_app_number] => 17/858336 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 44490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858336 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858336
TRANSPARENT PACKAGE FOR USE WITH PRINTED CIRCUIT BOARDS Jul 5, 2022 Pending
Array ( [id] => 17900780 [patent_doc_number] => 20220310442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => INTERCONNECT STRUCTURES INCLUDING AIR GAPS [patent_app_type] => utility [patent_app_number] => 17/806726 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6902 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806726 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806726
Interconnect structures including air gaps Jun 12, 2022 Issued
Array ( [id] => 17886843 [patent_doc_number] => 20220302321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => THIN FILM TRANSISTOR ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/831987 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831987 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831987
THIN FILM TRANSISTOR ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE Jun 2, 2022 Pending
Array ( [id] => 19351429 [patent_doc_number] => 20240260393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => Organic Electroluminescent Device [patent_app_type] => utility [patent_app_number] => 18/290010 [patent_app_country] => US [patent_app_date] => 2022-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18290010 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/290010
Organic Electroluminescent Device May 29, 2022 Pending
Array ( [id] => 17840650 [patent_doc_number] => 20220277956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => Treatment to Control Deposition Rate [patent_app_type] => utility [patent_app_number] => 17/749324 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749324 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749324
Treatment to Control Deposition Rate May 19, 2022 Pending
Array ( [id] => 18729310 [patent_doc_number] => 20230343606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR PACKAGES USING DIELECTRIC ALIGNMENT MARKS AND LASER LIFTOFF PROCESS [patent_app_type] => utility [patent_app_number] => 17/727495 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5529 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17727495 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/727495
METHOD FOR FORMING SEMICONDUCTOR PACKAGES USING DIELECTRIC ALIGNMENT MARKS AND LASER LIFTOFF PROCESS Apr 21, 2022 Issued
Array ( [id] => 17752708 [patent_doc_number] => 20220230913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH COVERING LINERS [patent_app_type] => utility [patent_app_number] => 17/716117 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17716117 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/716117
Method for fabricating semiconductor device with covering liners Apr 7, 2022 Issued
Array ( [id] => 17720200 [patent_doc_number] => 20220212920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => LIQUID-RESISTANT AIR INLET PASSIVE DEVICE AND METHODS OF MAKING SAME [patent_app_type] => utility [patent_app_number] => 17/701380 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701380 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701380
LIQUID-RESISTANT AIR INLET PASSIVE DEVICE AND METHODS OF MAKING SAME Mar 21, 2022 Abandoned
Array ( [id] => 19957374 [patent_doc_number] => 12327793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Semiconductor device with adjustment layers and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/698564 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 3354 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17698564 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/698564
Semiconductor device with adjustment layers and method for fabricating the same Mar 17, 2022 Issued
Array ( [id] => 18267622 [patent_doc_number] => 20230088864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/687379 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 414 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17687379 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/687379
Semiconductor memory device Mar 3, 2022 Issued
Array ( [id] => 18615835 [patent_doc_number] => 20230282574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => INTERCONNECT FEATURE CONTACTED WITHIN A RECESS [patent_app_type] => utility [patent_app_number] => 17/685539 [patent_app_country] => US [patent_app_date] => 2022-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685539 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685539
INTERCONNECT FEATURE CONTACTED WITHIN A RECESS Mar 2, 2022 Pending
Array ( [id] => 18379702 [patent_doc_number] => 20230154791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/679234 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17679234 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/679234
INTERCONNECTION STRUCTURE AND METHODS OF FORMING THE SAME Feb 23, 2022 Pending
Array ( [id] => 18123493 [patent_doc_number] => 20230009103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/650843 [patent_app_country] => US [patent_app_date] => 2022-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650843 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/650843
Bit line spacer structures including air gaps and method for forming the same Feb 11, 2022 Issued
Array ( [id] => 18593331 [patent_doc_number] => 11742242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Method for manufacturing through-silicon via with liner [patent_app_type] => utility [patent_app_number] => 17/584383 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3265 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17584383 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/584383
Method for manufacturing through-silicon via with liner Jan 25, 2022 Issued
Array ( [id] => 18026389 [patent_doc_number] => 20220377888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => TRANSPARENT PACKAGE FOR USE WITH PRINTED CIRCUIT BOARDS [patent_app_type] => utility [patent_app_number] => 17/579974 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17579974 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/579974
TRANSPARENT PACKAGE FOR USE WITH PRINTED CIRCUIT BOARDS Jan 19, 2022 Abandoned
Array ( [id] => 17870873 [patent_doc_number] => 20220293610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/575815 [patent_app_country] => US [patent_app_date] => 2022-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575815 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575815
MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE Jan 13, 2022 Pending
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