Search

Daniel M. Luke

Examiner (ID: 10322, Phone: (571)270-1569 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813, 2896
Total Applications
866
Issued Applications
580
Pending Applications
69
Abandoned Applications
228

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20638078 [patent_doc_number] => 12598977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Fill of vias in single and dual damascene structures using self-assembled monolayer [patent_app_type] => utility [patent_app_number] => 17/558423 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 5514 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558423 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/558423
Fill of vias in single and dual damascene structures using self-assembled monolayer Dec 20, 2021 Issued
Array ( [id] => 20267048 [patent_doc_number] => 12438047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Double patterning with selectively deposited spacer [patent_app_type] => utility [patent_app_number] => 17/555420 [patent_app_country] => US [patent_app_date] => 2021-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555420 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555420
Double patterning with selectively deposited spacer Dec 17, 2021 Issued
Array ( [id] => 18423957 [patent_doc_number] => 20230178421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => SUBTRACTIVE LINE WITH DAMASCENE TOP VIA [patent_app_type] => utility [patent_app_number] => 17/544136 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544136 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544136
SUBTRACTIVE LINE WITH DAMASCENE TOP VIA Dec 6, 2021 Abandoned
Array ( [id] => 19957302 [patent_doc_number] => 12327719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Semiconductor substrate polishing method [patent_app_type] => utility [patent_app_number] => 17/529355 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529355 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/529355
Semiconductor substrate polishing method Nov 17, 2021 Issued
Array ( [id] => 18943479 [patent_doc_number] => 20240038618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => SEMICONDUCTOR MODULE COMPRISING AT LEAST ONE SEMICONDUCTOR ELEMENT [patent_app_type] => utility [patent_app_number] => 18/265905 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18265905 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/265905
SEMICONDUCTOR MODULE COMPRISING AT LEAST ONE SEMICONDUCTOR ELEMENT Nov 2, 2021 Pending
Array ( [id] => 17431689 [patent_doc_number] => 20220059398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP [patent_app_type] => utility [patent_app_number] => 17/516696 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17516696 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/516696
Method for preparing semiconductor device structure with air gap Nov 1, 2021 Issued
Array ( [id] => 19288095 [patent_doc_number] => 20240224578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => ELECTROLUMINESCENT DEVICE AND DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/556850 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18556850 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/556850
ELECTROLUMINESCENT DEVICE AND DISPLAY APPARATUS Oct 21, 2021 Pending
Array ( [id] => 17347274 [patent_doc_number] => 20220013605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/486164 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486164 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/486164
Display apparatus having self-aligned structures Sep 26, 2021 Issued
Array ( [id] => 18265178 [patent_doc_number] => 20230086420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => SELF ALIGNED QUADRUPLE PATTERNING INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 17/479660 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479660 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/479660
SELF ALIGNED QUADRUPLE PATTERNING INTERCONNECTS Sep 19, 2021 Abandoned
Array ( [id] => 17318934 [patent_doc_number] => 20210407984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => FABRICATING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/472705 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472705 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472705
Fabricating method of semiconductor device with exposed input/output pad in recess Sep 12, 2021 Issued
Array ( [id] => 18222507 [patent_doc_number] => 20230061501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/458884 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8704 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458884 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/458884
Semiconductor device structure having air gap and methods of forming the same Aug 26, 2021 Issued
Array ( [id] => 18156203 [patent_doc_number] => 11569196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Chip to chip interconnect in encapsulant of molded semiconductor package [patent_app_type] => utility [patent_app_number] => 17/412787 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5127 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412787 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412787
Chip to chip interconnect in encapsulant of molded semiconductor package Aug 25, 2021 Issued
Array ( [id] => 17523065 [patent_doc_number] => 20220108914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => Treatment methods for titanium nitride films [patent_app_type] => utility [patent_app_number] => 17/398899 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398899 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/398899
Treatment methods for titanium nitride films Aug 9, 2021 Issued
Array ( [id] => 17247213 [patent_doc_number] => 20210366958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/392733 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9161 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17392733 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/392733
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD Aug 2, 2021 Abandoned
Array ( [id] => 17993226 [patent_doc_number] => 20220359263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Devices with Reduced Capacitances [patent_app_type] => utility [patent_app_number] => 17/382873 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382873 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/382873
Devices with reduced capacitances Jul 21, 2021 Issued
Array ( [id] => 17203486 [patent_doc_number] => 20210343581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/373885 [patent_app_country] => US [patent_app_date] => 2021-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17373885 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/373885
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME Jul 12, 2021 Abandoned
Array ( [id] => 17347078 [patent_doc_number] => 20220013409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => METHOD FOR MANUFACTURING WIRING SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/361522 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8241 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361522 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361522
Method for manufacturing wiring substrate Jun 28, 2021 Issued
Array ( [id] => 17115570 [patent_doc_number] => 20210296167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => METHODS FOR RELIABLY FORMING MICROELECTRONIC DEVICES WITH CONDUCTIVE CONTACTS TO SILICIDE REGIONS, AND RELATED SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/340410 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340410 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340410
Methods for reliably forming microelectronic devices with conductive contacts to silicide regions Jun 6, 2021 Issued
Array ( [id] => 17085776 [patent_doc_number] => 20210280783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => STEP HEIGHT MITIGATION IN RESISTIVE RANDOM ACCESS MEMORY STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/329247 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17329247 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/329247
Step height mitigation in resistive random access memory structures May 24, 2021 Issued
Array ( [id] => 17053934 [patent_doc_number] => 20210263368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/317890 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317890 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317890
DISPLAY DEVICE May 11, 2021 Abandoned
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