Search

Daniel M. Luke

Examiner (ID: 10322, Phone: (571)270-1569 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813, 2896
Total Applications
866
Issued Applications
580
Pending Applications
69
Abandoned Applications
228

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18008451 [patent_doc_number] => 20220367218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => SUBSTRATE PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/770653 [patent_app_country] => US [patent_app_date] => 2020-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17770653 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/770653
Substrate processing method including thickness monitoring Oct 14, 2020 Issued
Array ( [id] => 19093914 [patent_doc_number] => 11955379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Metal adhesion layer to promote metal plug adhesion [patent_app_type] => utility [patent_app_number] => 17/021776 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6957 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17021776 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/021776
Metal adhesion layer to promote metal plug adhesion Sep 14, 2020 Issued
Array ( [id] => 17115678 [patent_doc_number] => 20210296275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THEREOF [patent_app_type] => utility [patent_app_number] => 17/017464 [patent_app_country] => US [patent_app_date] => 2020-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17017464 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/017464
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THEREOF Sep 9, 2020 Abandoned
Array ( [id] => 19016349 [patent_doc_number] => 11923291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Via connection to wiring in a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/007626 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 7717 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007626 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007626
Via connection to wiring in a semiconductor device Aug 30, 2020 Issued
Array ( [id] => 17787721 [patent_doc_number] => 11410855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Method of producing electroconductive substrate, electronic device and display device [patent_app_type] => utility [patent_app_number] => 16/997092 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 31 [patent_no_of_words] => 11159 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997092 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/997092
Method of producing electroconductive substrate, electronic device and display device Aug 18, 2020 Issued
Array ( [id] => 16920414 [patent_doc_number] => 20210193506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => BILAYER SEAL MATERIAL FOR AIR GAPS IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/937237 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937237 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/937237
Bilayer seal material for air gaps in semiconductor devices Jul 22, 2020 Issued
Array ( [id] => 16601528 [patent_doc_number] => 20210028059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => Method for Forming a Buried Metal Line in a Semiconductor Substrate [patent_app_type] => utility [patent_app_number] => 16/934200 [patent_app_country] => US [patent_app_date] => 2020-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5389 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16934200 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/934200
Method for Forming a Buried Metal Line in a Semiconductor Substrate Jul 20, 2020 Abandoned
Array ( [id] => 18263102 [patent_doc_number] => 11610811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Semiconductor device with covering liners and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/902692 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 9328 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16902692 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/902692
Semiconductor device with covering liners and method for fabricating the same Jun 15, 2020 Issued
Array ( [id] => 17277942 [patent_doc_number] => 20210384140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => SEMICONDUCTOR DEVICE WITH ADJUSTMENT LAYERS AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/895620 [patent_app_country] => US [patent_app_date] => 2020-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16895620 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/895620
SEMICONDUCTOR DEVICE WITH ADJUSTMENT LAYERS AND METHOD FOR FABRICATING THE SAME Jun 7, 2020 Abandoned
Array ( [id] => 17262794 [patent_doc_number] => 20210375779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/885278 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16885278 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/885278
Damascene process using cap layer May 27, 2020 Issued
Array ( [id] => 16286379 [patent_doc_number] => 20200279981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => METHOD OF MANUFACTURING LIGHT EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 16/878241 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16878241 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/878241
Method for attaching light transmissive member to light emitting element May 18, 2020 Issued
Array ( [id] => 17247020 [patent_doc_number] => 20210366765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => VIA STRUCTURE AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/877670 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16877670 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/877670
Via structure and methods for forming the same May 18, 2020 Issued
Array ( [id] => 16257015 [patent_doc_number] => 20200266390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => ORGANIC LIGHT EMITTING DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/868217 [patent_app_country] => US [patent_app_date] => 2020-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868217 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/868217
Organic light emitting display device May 5, 2020 Issued
Array ( [id] => 16256790 [patent_doc_number] => 20200266165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => COPPER PILLARS HAVING IMPROVED INTEGRITY AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/866709 [patent_app_country] => US [patent_app_date] => 2020-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9032 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16866709 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/866709
COPPER PILLARS HAVING IMPROVED INTEGRITY AND METHODS OF MAKING THE SAME May 4, 2020 Abandoned
Array ( [id] => 16241640 [patent_doc_number] => 20200258874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => ISOLATOR INTEGRATED CIRCUITS WITH PACKAGE STRUCTURE CAVITY AND FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 16/859345 [patent_app_country] => US [patent_app_date] => 2020-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 491 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16859345 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/859345
Isolator integrated circuits with package structure cavity and fabrication methods Apr 26, 2020 Issued
Array ( [id] => 17156529 [patent_doc_number] => 20210317580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => METHOD OF DIELECTRIC MATERIAL FILL AND TREATMENT [patent_app_type] => utility [patent_app_number] => 16/848784 [patent_app_country] => US [patent_app_date] => 2020-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16848784 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/848784
Method of dielectric material fill and treatment Apr 13, 2020 Issued
Array ( [id] => 17517011 [patent_doc_number] => 11296172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/842862 [patent_app_country] => US [patent_app_date] => 2020-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6535 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16842862 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/842862
Semiconductor device Apr 7, 2020 Issued
Array ( [id] => 17115575 [patent_doc_number] => 20210296172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => FULLY ALIGNED INTERCONNECTS WITH SELECTIVE AREA DEPOSITION [patent_app_type] => utility [patent_app_number] => 16/826566 [patent_app_country] => US [patent_app_date] => 2020-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16826566 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/826566
Fully aligned interconnects with selective area deposition Mar 22, 2020 Issued
Array ( [id] => 17070627 [patent_doc_number] => 20210272844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/807138 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807138 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/807138
Liner for through-silicon via Mar 1, 2020 Issued
Array ( [id] => 19952904 [patent_doc_number] => 12324292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Apparatus and method for self-assembly of semiconductor light-emitting element [patent_app_type] => utility [patent_app_number] => 17/793882 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17793882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/793882
Apparatus and method for self-assembly of semiconductor light-emitting element Feb 12, 2020 Issued
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