Search

Daniel P. Stephenson

Examiner (ID: 2361, Phone: (571)272-7035 , Office: P/3676 )

Most Active Art Unit
3676
Art Unit(s)
3672, 3673, 3676
Total Applications
1976
Issued Applications
1654
Pending Applications
110
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11292405 [patent_doc_number] => 20160342337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'METHOD AND APPARATUS FOR SCALING OUT STORAGE DEVICES AND SCALED-OUT STORAGE DEVICES' [patent_app_type] => utility [patent_app_number] => 15/095969 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7775 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15095969 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/095969
Method and apparatus for scaling out storage devices and scaled-out storage devices Apr 10, 2016 Issued
Array ( [id] => 11629456 [patent_doc_number] => 20170139645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'MEMORY SYSTEM AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/096119 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 15721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15096119 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/096119
Memory system and operating method thereof using segment lists Apr 10, 2016 Issued
Array ( [id] => 11629457 [patent_doc_number] => 20170139646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'MEMORY SYSTEM AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/096160 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13597 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15096160 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/096160
Memory system and operating method thereof using a bitmap for filtering of logical addresses Apr 10, 2016 Issued
Array ( [id] => 11989402 [patent_doc_number] => 20170293557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'DECREASING THE DATA HANDOFF INTERVAL IN A MULTIPROCESSOR DATA PROCESSING SYSTEM BASED ON AN EARLY INDICATION OF A SYSTEMWIDE COHERENCE RESPONSE' [patent_app_type] => utility [patent_app_number] => 15/095642 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15095642 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/095642
Decreasing the data handoff interval in a multiprocessor data processing system based on an early indication of a systemwide coherence response Apr 10, 2016 Issued
Array ( [id] => 14299191 [patent_doc_number] => 10289722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => System and methods for multi-level key-value store [patent_app_type] => utility [patent_app_number] => 15/096267 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 14701 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15096267 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/096267
System and methods for multi-level key-value store Apr 10, 2016 Issued
Array ( [id] => 13068761 [patent_doc_number] => 10055160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Systems and methods for BIOS emulation of PCIe device [patent_app_type] => utility [patent_app_number] => 15/095980 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3095 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15095980 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/095980
Systems and methods for BIOS emulation of PCIe device Apr 10, 2016 Issued
Array ( [id] => 14735831 [patent_doc_number] => 10387315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Region migration cache [patent_app_type] => utility [patent_app_number] => 15/095778 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 8175 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15095778 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/095778
Region migration cache Apr 10, 2016 Issued
Array ( [id] => 14250313 [patent_doc_number] => 10275357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => System and methods for adaptive multi-level cache allocation for KV store [patent_app_type] => utility [patent_app_number] => 15/096255 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 14688 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15096255 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/096255
System and methods for adaptive multi-level cache allocation for KV store Apr 10, 2016 Issued
Array ( [id] => 11989332 [patent_doc_number] => 20170293487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'FLEXIBLE FRAMEWORK TO SUPPORT MEMORY SYNCHRONIZATION OPERATIONS' [patent_app_type] => utility [patent_app_number] => 15/096205 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15096205 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/096205
Flexible framework to support memory synchronization operations Apr 10, 2016 Issued
Array ( [id] => 11823760 [patent_doc_number] => 20170212698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'COMPUTING SYSTEM WITH CACHE STORING MECHANISM AND METHOD OF OPERATION THEREOF' [patent_app_type] => utility [patent_app_number] => 15/096261 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15096261 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/096261
COMPUTING SYSTEM WITH CACHE STORING MECHANISM AND METHOD OF OPERATION THEREOF Apr 10, 2016 Abandoned
Array ( [id] => 11027312 [patent_doc_number] => 20160224268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'EXTENDIBLE INPUT/OUTPUT DATA MECHANISM FOR ACCELERATORS' [patent_app_type] => utility [patent_app_number] => 15/092732 [patent_app_country] => US [patent_app_date] => 2016-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15092732 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/092732
Extendible input/output data mechanism for accelerators Apr 6, 2016 Issued
Array ( [id] => 11752382 [patent_doc_number] => 09710394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Translation entry invalidation in a multithreaded data processing system' [patent_app_type] => utility [patent_app_number] => 15/083469 [patent_app_country] => US [patent_app_date] => 2016-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 11758 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15083469 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/083469
Translation entry invalidation in a multithreaded data processing system Mar 28, 2016 Issued
Array ( [id] => 16385667 [patent_doc_number] => 10810508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-20 [patent_title] => Methods and apparatus for classifying and discovering historical and future operational states based on Boolean and numerical sensor data [patent_app_type] => utility [patent_app_number] => 15/076774 [patent_app_country] => US [patent_app_date] => 2016-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 7798 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 422 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15076774 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/076774
Methods and apparatus for classifying and discovering historical and future operational states based on Boolean and numerical sensor data Mar 21, 2016 Issued
Array ( [id] => 15284177 [patent_doc_number] => 10514751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Cache dormant indication [patent_app_type] => utility [patent_app_number] => 15/040440 [patent_app_country] => US [patent_app_date] => 2016-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5259 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15040440 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/040440
Cache dormant indication Feb 9, 2016 Issued
Array ( [id] => 13017111 [patent_doc_number] => 10031670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Control unit and control method for controlling writes and background operations of multiple semiconductor storage devices [patent_app_type] => utility [patent_app_number] => 15/040431 [patent_app_country] => US [patent_app_date] => 2016-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 14412 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15040431 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/040431
Control unit and control method for controlling writes and background operations of multiple semiconductor storage devices Feb 9, 2016 Issued
Array ( [id] => 11314102 [patent_doc_number] => 20160350212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'APPLICATION PROCESSOR AND A MOBILE APPARATUS HAVING A PLURALITY OF ADDRESS MAPPING FORMATS AND METHOD OF ACCESSING DATA INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/040296 [patent_app_country] => US [patent_app_date] => 2016-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8278 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15040296 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/040296
Application processor and a mobile apparatus having a plurality of address mapping formats and method of accessing data including the same Feb 9, 2016 Issued
Array ( [id] => 11020116 [patent_doc_number] => 20160217070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'PROCESSING UNIT RECLAIMING REQUESTS IN A SOLID STATE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/006430 [patent_app_country] => US [patent_app_date] => 2016-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15006430 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/006430
Processing unit reclaiming requests in a solid state memory device Jan 25, 2016 Issued
Array ( [id] => 11285540 [patent_doc_number] => 09501395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-22 [patent_title] => 'Re-aligning a compressed data array' [patent_app_type] => utility [patent_app_number] => 15/004462 [patent_app_country] => US [patent_app_date] => 2016-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10968 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15004462 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/004462
Re-aligning a compressed data array Jan 21, 2016 Issued
Array ( [id] => 10616706 [patent_doc_number] => 09336152 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-10 [patent_title] => 'Method and system for determining FIFO cache size' [patent_app_type] => utility [patent_app_number] => 15/002283 [patent_app_country] => US [patent_app_date] => 2016-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5854 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15002283 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/002283
Method and system for determining FIFO cache size Jan 19, 2016 Issued
Array ( [id] => 10999127 [patent_doc_number] => 20160196074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-07 [patent_title] => 'DATA ARRANGEMENT APPARATUS, STORAGE MEDIUM, AND DATA ARRANGEMENT METHOD' [patent_app_type] => utility [patent_app_number] => 14/977925 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10214 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977925 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977925
DATA ARRANGEMENT APPARATUS, STORAGE MEDIUM, AND DATA ARRANGEMENT METHOD Dec 21, 2015 Abandoned
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