Search

Daniel Pm Wicklund

Examiner (ID: 912, Phone: (571)270-7508 , Office: P/2833 )

Most Active Art Unit
2833
Art Unit(s)
2833, 2844
Total Applications
376
Issued Applications
278
Pending Applications
0
Abandoned Applications
98

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13485373 [patent_doc_number] => 20180294229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => MANUFACTURING METHOD OF PACKAGE STRUCTURE HAVING EMBEDDED BONDING FILM [patent_app_type] => utility [patent_app_number] => 16/008045 [patent_app_country] => US [patent_app_date] => 2018-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16008045 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/008045
Manufacturing method of package structure having embedded bonding film Jun 13, 2018 Issued
Array ( [id] => 14367441 [patent_doc_number] => 10305036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Thermally optimized phase change memory cells and methods of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/994815 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 11739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15994815 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/994815
Thermally optimized phase change memory cells and methods of fabricating the same May 30, 2018 Issued
Array ( [id] => 16495718 [patent_doc_number] => 10861767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Package structure with multiple substrates [patent_app_type] => utility [patent_app_number] => 15/993169 [patent_app_country] => US [patent_app_date] => 2018-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 6921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15993169 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/993169
Package structure with multiple substrates May 29, 2018 Issued
Array ( [id] => 14205067 [patent_doc_number] => 10269655 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-23 [patent_title] => Semiconductor device and method [patent_app_type] => utility [patent_app_number] => 15/993252 [patent_app_country] => US [patent_app_date] => 2018-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 10004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15993252 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/993252
Semiconductor device and method May 29, 2018 Issued
Array ( [id] => 14616777 [patent_doc_number] => 10361095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Metal interconnect processing for an integrated circuit metal stack [patent_app_type] => utility [patent_app_number] => 15/981725 [patent_app_country] => US [patent_app_date] => 2018-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3006 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981725 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/981725
Metal interconnect processing for an integrated circuit metal stack May 15, 2018 Issued
Array ( [id] => 14769363 [patent_doc_number] => 10396083 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/974943 [patent_app_country] => US [patent_app_date] => 2018-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 9943 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15974943 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/974943
Semiconductor devices May 8, 2018 Issued
Array ( [id] => 13528135 [patent_doc_number] => 20180315610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => WAFER PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 15/964396 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964396 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964396
Wafer processing method Apr 26, 2018 Issued
Array ( [id] => 14859215 [patent_doc_number] => 10418342 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-17 [patent_title] => Silicon strip fan out system in package [patent_app_type] => utility [patent_app_number] => 15/963678 [patent_app_country] => US [patent_app_date] => 2018-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 1774 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15963678 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/963678
Silicon strip fan out system in package Apr 25, 2018 Issued
Array ( [id] => 14333361 [patent_doc_number] => 10297710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Method of processing wafer [patent_app_type] => utility [patent_app_number] => 15/962772 [patent_app_country] => US [patent_app_date] => 2018-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5761 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15962772 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/962772
Method of processing wafer Apr 24, 2018 Issued
Array ( [id] => 14769145 [patent_doc_number] => 10395974 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-27 [patent_title] => Method for forming a thin semiconductor-on-insulator (SOI) substrate [patent_app_type] => utility [patent_app_number] => 15/962214 [patent_app_country] => US [patent_app_date] => 2018-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 11004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15962214 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/962214
Method for forming a thin semiconductor-on-insulator (SOI) substrate Apr 24, 2018 Issued
Array ( [id] => 13283455 [patent_doc_number] => 10153319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => CMOS image sensor with dual damascene grid design having absorption enhancement structure [patent_app_type] => utility [patent_app_number] => 15/960780 [patent_app_country] => US [patent_app_date] => 2018-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15960780 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/960780
CMOS image sensor with dual damascene grid design having absorption enhancement structure Apr 23, 2018 Issued
Array ( [id] => 13364123 [patent_doc_number] => 20180233601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => TRANSISTOR AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/952433 [patent_app_country] => US [patent_app_date] => 2018-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15952433 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/952433
Transistor and semiconductor device Apr 12, 2018 Issued
Array ( [id] => 14125339 [patent_doc_number] => 10249533 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-02 [patent_title] => Method and structure for forming a replacement contact [patent_app_type] => utility [patent_app_number] => 15/951787 [patent_app_country] => US [patent_app_date] => 2018-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5709 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15951787 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/951787
Method and structure for forming a replacement contact Apr 11, 2018 Issued
Array ( [id] => 13499581 [patent_doc_number] => 20180301333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => Method And Apparatus For Deposition Of Low-K Films [patent_app_type] => utility [patent_app_number] => 15/951655 [patent_app_country] => US [patent_app_date] => 2018-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15951655 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/951655
Method and apparatus for deposition of low-k films Apr 11, 2018 Issued
Array ( [id] => 15169849 [patent_doc_number] => 10490428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Method and system for dual stretching of wafers for isolated segmented chip scale packages [patent_app_type] => utility [patent_app_number] => 15/951775 [patent_app_country] => US [patent_app_date] => 2018-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3009 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15951775 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/951775
Method and system for dual stretching of wafers for isolated segmented chip scale packages Apr 11, 2018 Issued
Array ( [id] => 13514303 [patent_doc_number] => 20180308694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => Selective Deposition Of Tungsten For Simplified Process Flow Of Tungsten Oxide Pillar Formation [patent_app_type] => utility [patent_app_number] => 15/951726 [patent_app_country] => US [patent_app_date] => 2018-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15951726 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/951726
Selective deposition for simplified process flow of pillar formation Apr 11, 2018 Issued
Array ( [id] => 14738901 [patent_doc_number] => 10388862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-20 [patent_title] => Highly selective ion beam etch hard mask for sub 60nm MRAM devices [patent_app_type] => utility [patent_app_number] => 15/951873 [patent_app_country] => US [patent_app_date] => 2018-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2677 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15951873 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/951873
Highly selective ion beam etch hard mask for sub 60nm MRAM devices Apr 11, 2018 Issued
Array ( [id] => 15733435 [patent_doc_number] => 10615154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods [patent_app_type] => utility [patent_app_number] => 15/941611 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5492 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15941611 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/941611
Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods Mar 29, 2018 Issued
Array ( [id] => 13306407 [patent_doc_number] => 20180204740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => SYSTEM AND METHOD FOR LASER ASSISTED BONDING OF SEMICONDUCTOR DIE [patent_app_type] => utility [patent_app_number] => 15/919569 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919569 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/919569
System and method for laser assisted bonding of semiconductor die Mar 12, 2018 Issued
Array ( [id] => 12917845 [patent_doc_number] => 20180197791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => Semiconductor Devices Having FIN Active Regions [patent_app_type] => utility [patent_app_number] => 15/914125 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914125 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/914125
Semiconductor devices having FIN active regions Mar 6, 2018 Issued
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